restructuring to improve workflow

Former-commit-id: 95a0dbd49c62279dd63d9134f95b583c05e3b6e6 [formerly e0713d8da8283e5ed06627281734acfb31a80095]
Former-commit-id: a22bf939a28c44dd7ea718feedb8f91be99718f6

disassembly/GE007.rom.asm

@@ -6,3 +6,9 @@ origin $00000000
 
 include "rom/romheader.asm"
 include "boot.asm"
+include "libultra_rom.asm"
+include "rarezip/rarezip.asm"
+include "rodata/rodata.asm"
+include "bss/bss.asm"
+include "bss/80300000.asm"
+

disassembly/boot.asm.REMOVED.git-id

@@ -1 +1 @@
-189c63b6c85410327b1fd7a71d7fc0069edcd7fe
+93f6a3080e47f9c3bb8ff570b426b3e1a519b3cc

disassembly/bss/80300000.asm

@@ -0,0 +1,20 @@
+base $80300000
+decompression_buffer:
+
+base $803AB400
+sp_boot:
+
+base $803AB410
+sp_rmon:
+
+base $803AB710
+sp_idle:
+
+base $803AB750
+sp_shed:
+
+base $803AB950
+sp_main:
+
+base $803B3950
+sp_audi:

disassembly/bss/bss.asm

@@ -0,0 +1,5 @@
+base $8005D2E0
+bss_start:
+
+base $8008E360
+bss_end:

disassembly/libultra_rom.asm

@@ -0,0 +1,23 @@
+base $7000CF90    
+osPiRawStartDma:
+
+base $7000D320
+osWritebackDCacheAll:
+
+base $7000D350
+osInvalICache:
+
+base $7000D3D0
+osUnmapTLB:
+
+base $7000D410
+__osGetFpcCsr:
+
+base $7000D420
+__osSetFpcCsr:
+
+base $7000D430
+osCreateThread:
+
+base $7000D580
+osStartThread:

disassembly/rarezip/rarezip.asm

@@ -0,0 +1,5 @@
+base $70200000
+RareZip_vaddr:
+
+base $7020141C
+decompressfile:

disassembly/rodata/rodata.asm

@@ -1,5 +1,9 @@
-arch n64.cpu
-endian msb
-output "rodata.bin", create
+//arch n64.cpu
+//endian msb
+//output "rodata.bin", create
 base $80020D90
-insert rsp.bin, "rsp.bin"
+rodata_start:
+//insert rsp.bin, "rsp.bin"
+
+base $8005D2E0
+rodata_end: