137 lines
5.6 KiB
ArmAsm
137 lines
5.6 KiB
ArmAsm
#include <sys/asm.h>
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#include <PR/rcp.h>
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.include "macro.inc"
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# assembler directives
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.set noat # allow manual use of $at
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.set gp=64 # allow use of 64-bit general purpose registers
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.rdata
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#define MI_INTR_MASK 0x3f
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#define CLR_SP 0x0001
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#define SET_SP 0x0002
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#define CLR_SI 0x0004
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#define SET_SI 0x0008
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#define CLR_AI 0x0010
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#define SET_AI 0x0020
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#define CLR_VI 0x0040
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#define SET_VI 0x0080
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#define CLR_PI 0x0100
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#define SET_PI 0x0200
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#define CLR_DP 0x0400
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#define SET_DP 0x0800
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EXPORT(__osRcpImTable)
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/* LUT to convert between MI_INTR and MI_INTR_MASK */
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/* MI_INTR is status for each interrupt whereas */
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/* MI_INTR_MASK has seperate bits for set/clr */
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.half CLR_SP | CLR_SI | CLR_AI | CLR_VI | CLR_PI | CLR_DP
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.half SET_SP | CLR_SI | CLR_AI | CLR_VI | CLR_PI | CLR_DP
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.half CLR_SP | SET_SI | CLR_AI | CLR_VI | CLR_PI | CLR_DP
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.half SET_SP | SET_SI | CLR_AI | CLR_VI | CLR_PI | CLR_DP
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.half CLR_SP | CLR_SI | SET_AI | CLR_VI | CLR_PI | CLR_DP
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.half SET_SP | CLR_SI | SET_AI | CLR_VI | CLR_PI | CLR_DP
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.half CLR_SP | SET_SI | SET_AI | CLR_VI | CLR_PI | CLR_DP
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.half SET_SP | SET_SI | SET_AI | CLR_VI | CLR_PI | CLR_DP
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.half CLR_SP | CLR_SI | CLR_AI | SET_VI | CLR_PI | CLR_DP
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.half SET_SP | CLR_SI | CLR_AI | SET_VI | CLR_PI | CLR_DP
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.half CLR_SP | SET_SI | CLR_AI | SET_VI | CLR_PI | CLR_DP
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.half SET_SP | SET_SI | CLR_AI | SET_VI | CLR_PI | CLR_DP
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.half CLR_SP | CLR_SI | SET_AI | SET_VI | CLR_PI | CLR_DP
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.half SET_SP | CLR_SI | SET_AI | SET_VI | CLR_PI | CLR_DP
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.half CLR_SP | SET_SI | SET_AI | SET_VI | CLR_PI | CLR_DP
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.half SET_SP | SET_SI | SET_AI | SET_VI | CLR_PI | CLR_DP
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.half CLR_SP | CLR_SI | CLR_AI | CLR_VI | SET_PI | CLR_DP
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.half SET_SP | CLR_SI | CLR_AI | CLR_VI | SET_PI | CLR_DP
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.half CLR_SP | SET_SI | CLR_AI | CLR_VI | SET_PI | CLR_DP
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.half SET_SP | SET_SI | CLR_AI | CLR_VI | SET_PI | CLR_DP
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.half CLR_SP | CLR_SI | SET_AI | CLR_VI | SET_PI | CLR_DP
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.half SET_SP | CLR_SI | SET_AI | CLR_VI | SET_PI | CLR_DP
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.half CLR_SP | SET_SI | SET_AI | CLR_VI | SET_PI | CLR_DP
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.half SET_SP | SET_SI | SET_AI | CLR_VI | SET_PI | CLR_DP
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.half CLR_SP | CLR_SI | CLR_AI | SET_VI | SET_PI | CLR_DP
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.half SET_SP | CLR_SI | CLR_AI | SET_VI | SET_PI | CLR_DP
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.half CLR_SP | SET_SI | CLR_AI | SET_VI | SET_PI | CLR_DP
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.half SET_SP | SET_SI | CLR_AI | SET_VI | SET_PI | CLR_DP
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.half CLR_SP | CLR_SI | SET_AI | SET_VI | SET_PI | CLR_DP
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.half SET_SP | CLR_SI | SET_AI | SET_VI | SET_PI | CLR_DP
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.half CLR_SP | SET_SI | SET_AI | SET_VI | SET_PI | CLR_DP
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.half SET_SP | SET_SI | SET_AI | SET_VI | SET_PI | CLR_DP
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.half CLR_SP | CLR_SI | CLR_AI | CLR_VI | CLR_PI | SET_DP
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.half SET_SP | CLR_SI | CLR_AI | CLR_VI | CLR_PI | SET_DP
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.half CLR_SP | SET_SI | CLR_AI | CLR_VI | CLR_PI | SET_DP
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.half SET_SP | SET_SI | CLR_AI | CLR_VI | CLR_PI | SET_DP
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.half CLR_SP | CLR_SI | SET_AI | CLR_VI | CLR_PI | SET_DP
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.half SET_SP | CLR_SI | SET_AI | CLR_VI | CLR_PI | SET_DP
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.half CLR_SP | SET_SI | SET_AI | CLR_VI | CLR_PI | SET_DP
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.half SET_SP | SET_SI | SET_AI | CLR_VI | CLR_PI | SET_DP
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.half CLR_SP | CLR_SI | CLR_AI | SET_VI | CLR_PI | SET_DP
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.half SET_SP | CLR_SI | CLR_AI | SET_VI | CLR_PI | SET_DP
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.half CLR_SP | SET_SI | CLR_AI | SET_VI | CLR_PI | SET_DP
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.half SET_SP | SET_SI | CLR_AI | SET_VI | CLR_PI | SET_DP
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.half CLR_SP | CLR_SI | SET_AI | SET_VI | CLR_PI | SET_DP
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.half SET_SP | CLR_SI | SET_AI | SET_VI | CLR_PI | SET_DP
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.half CLR_SP | SET_SI | SET_AI | SET_VI | CLR_PI | SET_DP
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.half SET_SP | SET_SI | SET_AI | SET_VI | CLR_PI | SET_DP
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.half CLR_SP | CLR_SI | CLR_AI | CLR_VI | SET_PI | SET_DP
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.half SET_SP | CLR_SI | CLR_AI | CLR_VI | SET_PI | SET_DP
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.half CLR_SP | SET_SI | CLR_AI | CLR_VI | SET_PI | SET_DP
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.half SET_SP | SET_SI | CLR_AI | CLR_VI | SET_PI | SET_DP
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.half CLR_SP | CLR_SI | SET_AI | CLR_VI | SET_PI | SET_DP
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.half SET_SP | CLR_SI | SET_AI | CLR_VI | SET_PI | SET_DP
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.half CLR_SP | SET_SI | SET_AI | CLR_VI | SET_PI | SET_DP
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.half SET_SP | SET_SI | SET_AI | CLR_VI | SET_PI | SET_DP
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.half CLR_SP | CLR_SI | CLR_AI | SET_VI | SET_PI | SET_DP
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.half SET_SP | CLR_SI | CLR_AI | SET_VI | SET_PI | SET_DP
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.half CLR_SP | SET_SI | CLR_AI | SET_VI | SET_PI | SET_DP
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.half SET_SP | SET_SI | CLR_AI | SET_VI | SET_PI | SET_DP
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.half CLR_SP | CLR_SI | SET_AI | SET_VI | SET_PI | SET_DP
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.half SET_SP | CLR_SI | SET_AI | SET_VI | SET_PI | SET_DP
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.half CLR_SP | SET_SI | SET_AI | SET_VI | SET_PI | SET_DP
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.half SET_SP | SET_SI | SET_AI | SET_VI | SET_PI | SET_DP
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.text
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.set noreorder
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glabel osSetIntMask
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mfc0 $t4, $12
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andi $v0, $t4, 0xff01
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lui $t0, %hi(__OSGlobalIntMask)
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addiu $t0, $t0, %lo(__OSGlobalIntMask)
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lw $t3, ($t0)
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addiu $at, $zero, -1
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xor $t0, $t3, $at
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andi $t0, $t0, 0xff00
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or $v0, $v0, $t0
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lui $t2, %hi(PHYS_TO_K1(MI_INTR_MASK_REG))
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lw $t2, %lo(PHYS_TO_K1(MI_INTR_MASK_REG))($t2)
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beqz $t2, setintmask_1
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srl $t1, $t3, 0x10
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addiu $at, $zero, -1
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xor $t1, $t1, $at
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andi $t1, $t1, 0x3f
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or $t2, $t2, $t1
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setintmask_1:
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sll $t2, $t2, 0x10
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or $v0, $v0, $t2
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lui $at, 0x3f
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and $t0, $a0, $at
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and $t0, $t0, $t3
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srl $t0, $t0, 0xf
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lui $t2, %hi(__osRcpImTable)
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addu $t2, $t2, $t0
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lhu $t2, %lo(__osRcpImTable)($t2)
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lui $at, %hi(PHYS_TO_K1(MI_INTR_MASK_REG))
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sw $t2, %lo(PHYS_TO_K1(MI_INTR_MASK_REG))($at)
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andi $t0, $a0, 0xff01
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andi $t1, $t3, 0xff00
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and $t0, $t0, $t1
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lui $at, 0xffff
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ori $at, $at, 0xff
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and $t4, $t4, $at
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or $t4, $t4, $t0
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mtc0 $t4, $12
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nop
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nop
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jr $ra
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nop
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endlabel osSetIntMask
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