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Fix maybe

This commit is contained in:
Tharo 2025-08-05 18:34:38 +01:00
parent 79fb045379
commit 2a94cb7a79
5 changed files with 5 additions and 45 deletions
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2
include/PR/rcp.h
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@ -532,6 +532,8 @@
#define VI_CTRL_PIXEL_ADV(n) (((n) << 12) & VI_CTRL_PIXEL_ADV_MASK) /* Bit [15:12] pixel advance mode: Always 3 on N64 */ #define VI_CTRL_PIXEL_ADV(n) (((n) << 12) & VI_CTRL_PIXEL_ADV_MASK) /* Bit [15:12] pixel advance mode: Always 3 on N64 */
#define VI_CTRL_DITHER_FILTER_ON 0x10000 /* 16: dither-filter mode */ #define VI_CTRL_DITHER_FILTER_ON 0x10000 /* 16: dither-filter mode */
#define VI_CTRL_PIXEL_ADV_3 VI_CTRL_PIXEL_ADV(3)
/* /*
* Possible video clocks (NTSC or PAL) * Possible video clocks (NTSC or PAL)
*/ */

43
include/PR/rdp.h
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@ -1,50 +1,7 @@
#ifndef PR_RDP_H #ifndef PR_RDP_H
#define PR_RDP_H #define PR_RDP_H
/* DP Command Registers */
#define DPC_START_REG 0x04100000
#define DPC_END_REG 0x04100004
#define DPC_CURRENT_REG 0x04100008
#define DPC_STATUS_REG 0x0410000C
#define DPC_CLOCK_REG 0x04100010
#define DPC_BUFBUSY_REG 0x04100014
#define DPC_PIPEBUSY_REG 0x04100018
#define DPC_TMEM_REG 0x0410001C
/* DP Span Registers */
#define DPS_TBIST_REG 0x04200000
#define DPS_TEST_MODE_REG 0x04200004
#define DPS_BUFTEST_ADDR_REG 0x04200008
#define DPS_BUFTEST_DATA_REG 0x0420000C
/* DP Status Read Flags */
#define DPC_STATUS_XBUS_DMEM_DMA (1 << 0)
#define DPC_STATUS_FREEZE (1 << 1)
#define DPC_STATUS_FLUSH (1 << 2)
#define DPC_STATUS_START_GCLK (1 << 3)
#define DPC_STATUS_TMEM_BUSY (1 << 4)
#define DPC_STATUS_PIPE_BUSY (1 << 5)
#define DPC_STATUS_CMD_BUSY (1 << 6)
#define DPC_STATUS_CBUF_READY (1 << 7)
#define DPC_STATUS_DMA_BUSY (1 << 8)
#define DPC_STATUS_END_VALID (1 << 9)
#define DPC_STATUS_START_VALID (1 << 10)
/* DP Status Write Flags */
#define DPC_CLR_XBUS_DMEM_DMA (1 << 0)
#define DPC_SET_XBUS_DMEM_DMA (1 << 1)
#define DPC_CLR_FREEZE (1 << 2)
#define DPC_SET_FREEZE (1 << 3)
#define DPC_CLR_FLUSH (1 << 4)
#define DPC_SET_FLUSH (1 << 5)
#define DPC_CLR_TMEM_CTR (1 << 6)
#define DPC_CLR_PIPE_CTR (1 << 7)
#define DPC_CLR_CMD_CTR (1 << 8)
#define DPC_CLR_CLOCK_CTR (1 << 9)
u32 osDpGetStatus(void); u32 osDpGetStatus(void);
void osDpSetStatus(u32 data); void osDpSetStatus(u32 data);
#endif #endif

1
include/ultra64.h
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@ -14,6 +14,7 @@
#include "PR/sptask.h" #include "PR/sptask.h"
#include "PR/rcp.h" #include "PR/rcp.h"
#include "PR/rdp.h" #include "PR/rdp.h"
#include "PR/os_internal_rsp.h"
#include "PR/R4300.h" #include "PR/R4300.h"
#include "PR/ucode.h" #include "PR/ucode.h"
#include "PR/viint.h" #include "PR/viint.h"

2
src/libultra/io/si.c
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@ -4,7 +4,7 @@
s32 __osSiDeviceBusy() { s32 __osSiDeviceBusy() {
register u32 status = IO_READ(SI_STATUS_REG); register u32 status = IO_READ(SI_STATUS_REG);
if (status & (SI_STATUS_DMA_BUSY | SI_STATUS_IO_READ_BUSY)) { if (status & (SI_STATUS_DMA_BUSY | SI_STATUS_RD_BUSY)) {
return true; return true;
} else { } else {
return false; return false;

2
src/libultra/io/sirawdma.c
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@ -2,7 +2,7 @@
#include "alignment.h" #include "alignment.h"
s32 __osSiRawStartDma(s32 direction, void* dramAddr) { s32 __osSiRawStartDma(s32 direction, void* dramAddr) {
if (IO_READ(SI_STATUS_REG) & (SI_STATUS_DMA_BUSY | SI_STATUS_IO_READ_BUSY)) { if (IO_READ(SI_STATUS_REG) & (SI_STATUS_DMA_BUSY | SI_STATUS_RD_BUSY)) {
return -1; return -1;
} }