mirror of https://github.com/zeldaret/mm.git
121 lines
4.2 KiB
Plaintext
121 lines
4.2 KiB
Plaintext
// libultra OS symbols
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D_80000000 = 0x80000000; // __osExceptionPreamble
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D_80000004 = 0x80000004; // __osExceptionPreamble
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D_80000008 = 0x80000008; // __osExceptionPreamble
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D_8000000C = 0x8000000C; // __osExceptionPreamble
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D_80000010 = 0x80000010; //
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D_80000020 = 0x80000020; //
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osTvType = 0x80000300;
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osRomType = 0x80000304;
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osRomBase = 0x80000308;
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osResetType = 0x8000030C;
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osCicId = 0x80000310;
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osVersion = 0x80000314;
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osMemSize = 0x80000318;
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osAppNMIBuffer = 0x8000031C;
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/// OS hardware registers
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// Signal Processor Registers
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D_A4040000 = 0xA4040000; // SP_MEM_ADDR_REG
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D_A4040004 = 0xA4040004; // SP_DRAM_ADDR_REG
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D_A4040008 = 0xA4040008; // SP_RD_LEN_REG
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D_A404000C = 0xA404000C; // SP_WR_LEN_REG
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D_A4040010 = 0xA4040010; // SP_STATUS_REG
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D_A4040014 = 0xA4040014; // SP_DMA_FULL_REG
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D_A4040018 = 0xA4040018; // SP_DMA_BUSY_REG
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D_A404001C = 0xA404001C; // SP_SEMAPHORE_REG
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D_A4080000 = 0xA4080000; // SP PC
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// Display Processor Command Registers / Rasterizer Interface
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D_A4100000 = 0xA4100000; // DPC_START_REG
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D_A4100004 = 0xA4100004; // DPC_END_REG
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D_A4100008 = 0xA4100008; // DPC_CURRENT_REG
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D_A410000C = 0xA410000C; // DPC_STATUS_REG
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D_A4100010 = 0xA4100010; // DPC_CLOCK_REG
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D_A4100014 = 0xA4100014; // DPC_BUFBUSY_REG
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D_A4100018 = 0xA4100018; // DPC_PIPEBUSY_REG
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D_A410001C = 0xA410001C; // DPC_TMEM_REG
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// Display Processor Span Registers
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D_A4200000 = 0xA4200000; // DPS_TBIST_REG / DP_TMEM_BIST
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D_A4200004 = 0xA4200004; // DPS_TEST_MODE_REG
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D_A4200008 = 0xA4200008; // DPS_BUFTEST_ADDR_REG
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D_A420000C = 0xA420000C; // DPS_BUFTEST_DATA_REG
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// MIPS Interface Registers
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D_A4300000 = 0xA4300000; // MI_MODE_REG / MI_INIT_MODE_REG
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D_A4300004 = 0xA4300004; // MI_VERSION_REG
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D_A4300008 = 0xA4300008; // MI_INTR_REG
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D_A430000C = 0xA430000C; // MI_INTR_MASK_REG
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// Video Interface Registers
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D_A4400000 = 0xA4400000; // VI_STATUS_REG / VI_CONTROL_REG
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D_A4400004 = 0xA4400004; // VI_DRAM_ADDR_REG / VI_ORIGIN_REG
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D_A4400008 = 0xA4400008; // VI_WIDTH_REG
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D_A440000C = 0xA440000C; // VI_INTR_REG
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D_A4400010 = 0xA4400010; // VI_CURRENT_REG
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D_A4400014 = 0xA4400014; // VI_BURST_REG / VI_TIMING_REG
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D_A4400018 = 0xA4400018; // VI_V_SYNC_REG
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D_A440001C = 0xA440001C; // VI_H_SYNC_REG
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D_A4400020 = 0xA4400020; // VI_LEAP_REG
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D_A4400024 = 0xA4400024; // VI_H_START_REG
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D_A4400028 = 0xA4400028; // VI_V_START_REG
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D_A440002C = 0xA440002C; // VI_V_BURST_REG
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D_A4400030 = 0xA4400030; // VI_X_SCALE_REG
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D_A4400034 = 0xA4400034; // VI_Y_SCALE_REG
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// Audio Interface Registers
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D_A4500000 = 0xA4500000; // AI_DRAM_ADDR_REG
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D_A4500004 = 0xA4500004; // AI_LEN_REG
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D_A4500008 = 0xA4500008; // AI_CONTROL_REG
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D_A450000C = 0xA450000C; // AI_STATUS_REG
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D_A4500010 = 0xA4500010; // AI_DACRATE_REG
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D_A4500014 = 0xA4500014; // AI_BITRATE_REG
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// Peripheral/Parallel Interface Registers
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D_A4600000 = 0xA4600000; // PI_DRAM_ADDR_REG
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D_A4600004 = 0xA4600004; // PI_CART_ADDR_REG
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D_A4600008 = 0xA4600008; // PI_RD_LEN_REG
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D_A460000C = 0xA460000C; // PI_WR_LEN_REG
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D_A4600010 = 0xA4600010; // PI_STATUS_REG
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D_A4600014 = 0xA4600014; // PI_BSD_DOM1_LAT_REG // PI dom1 latency
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D_A4600018 = 0xA4600018; // PI_BSD_DOM1_PWD_REG // PI dom1 pulse width
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D_A460001C = 0xA460001C; // PI_BSD_DOM1_PGS_REG // PI dom1 page size
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D_A4600020 = 0xA4600020; // PI_BSD_DOM1_RLS_REG // PI dom1 release
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D_A4600024 = 0xA4600024; // PI_BSD_DOM2_LAT_REG // PI dom2 latency
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D_A4600028 = 0xA4600028; // PI_BSD_DOM2_LWD_REG // PI dom2 pulse width
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D_A460002C = 0xA460002C; // PI_BSD_DOM2_PGS_REG // PI dom2 page size
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D_A4600030 = 0xA4600030; // PI_BSD_DOM2_RLS_REG // PI dom2 release
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// RDRAM Interface Registers
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D_A4700000 = 0xA4700000; // RI_MODE_REG
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D_A4700004 = 0xA4700004; // RI_CONFIG_REG
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D_A4700008 = 0xA4700008; // RI_CURRENT_LOAD_REG
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D_A470000C = 0xA470000C; // RI_SELECT_REG
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D_A4700010 = 0xA4700010; // RI_REFRESH_REG
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D_A4700014 = 0xA4700014; // RI_LATENCY_REG
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D_A4700018 = 0xA4700018; // RI_RERROR_REG
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D_A470001C = 0xA470001C; // RI_WERROR_REG
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// Serial Interface Registers
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D_A4800000 = 0xA4800000; // SI_DRAM_ADDR_REG
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D_A4800004 = 0xA4800004; // SI_PIF_ADDR_RD64B_REG
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D_A4800008 = 0xA4800008; // reserved
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D_A480000C = 0xA480000C; // reserved
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D_A4800010 = 0xA4800010; // SI_PIF_ADDR_WR64B_REG
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D_A4800014 = 0xA4800014; // reserved
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D_A4800018 = 0xA4800018; // SI_STATUS_REG
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