mirror of https://github.com/zeldaret/mm.git
103 lines
3.5 KiB
C
103 lines
3.5 KiB
C
#ifndef PR_RCP_H
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#define PR_RCP_H
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/**
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* PIF Physical memory map (total size = 2 KB)
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*
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* Size Description Mode
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* 1FC007FF +-------+-----------------+-----+
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* | 64 B | JoyChannel RAM | R/W |
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* 1FC007C0 +-------+-----------------+-----+
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* |1984 B | Boot ROM | * | * = Reserved
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* 1FC00000 +-------+-----------------+-----+
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*/
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#define PIF_ROM_START 0x1FC00000
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#define PIF_ROM_END 0x1FC007BF
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#define PIF_RAM_START 0x1FC007C0
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#define PIF_RAM_END 0x1FC007FF
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#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
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#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
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#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
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/**
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* Audio Interface (AI) Registers
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*/
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#define AI_BASE_REG 0x04500000
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/* AI DRAM address (W): [23:0] starting RDRAM address (8B-aligned) */
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#define AI_DRAM_ADDR_REG (AI_BASE_REG + 0x00) /* R0: DRAM address */
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/* AI length (R/W): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored */
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/* [17:0] transfer length (v2.0) - Bottom 3 bits are ignored */
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#define AI_LEN_REG (AI_BASE_REG + 0x04) /* R1: Length */
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/* AI control (W): [0] DMA enable - if LSB == 1, DMA is enabled */
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#define AI_CONTROL_REG (AI_BASE_REG + 0x08) /* R2: DMA Control */
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/* Value for control register */
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#define AI_CONTROL_DMA_ON 1 /* LSB = 1: DMA enable*/
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#define AI_CONTROL_DMA_OFF 0 /* LSB = 1: DMA enable*/
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/*
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* AI status (R): [31]/[0] ai_full (addr & len buffer full), [30] ai_busy
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* Note that a 1->0 transition in ai_full will set interrupt
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* (W): clear audio interrupt
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*/
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#define AI_STATUS_REG (AI_BASE_REG + 0x0C) /* R3: Status */
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/* Value for status register */
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#define AI_STATUS_FIFO_FULL (1 << 31)
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#define AI_STATUS_DMA_BUSY (1 << 30)
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/*
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* AI DAC sample period register (W): [13:0] dac rate
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* - vid_clock/(dperiod + 1) is the DAC sample rate
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* - (dperiod + 1) >= 66 * (aclockhp + 1) must be true
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*/
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#define AI_DACRATE_REG (AI_BASE_REG + 0x10) /* R4: DAC rate 14-lsb*/
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/* DAC rate = video clock / audio frequency
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* - DAC rate >= (66 * Bit rate) must be true
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*/
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#define AI_MAX_DAC_RATE 16384 /* 14-bit+1 */
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#define AI_MIN_DAC_RATE 132
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/*
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* AI bit rate (W): [3:0] bit rate (abus clock half period register - aclockhp)
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* - vid_clock/(2 * (aclockhp + 1)) is the DAC clock rate
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* - The abus clock stops if aclockhp is zero
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*/
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#define AI_BITRATE_REG (AI_BASE_REG + 0x14) /* R5: Bit rate 4-lsb */
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/* Bit rate <= (DAC rate / 66) */
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#define AI_MAX_BIT_RATE 16 /* 4-bit+1 */
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#define AI_MIN_BIT_RATE 2
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#define DEVICE_TYPE_CART 0 /* ROM cartridge */
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#define DEVICE_TYPE_BULK 1 /* ROM bulk */
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#define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */
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#define DEVICE_TYPE_SRAM 3 /* SRAM */
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#define DEVICE_TYPE_INIT 7 /* initial value */
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/**
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* Signal Processor (SP) Memory
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*/
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#define SP_DMEM_START 0x04000000
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#define SP_DMEM_END 0x04000FFF
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#define SP_IMEM_START 0x04001000
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#define SP_IMEM_END 0x04001FFF
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#define CHNL_ERR_NORESP 0x80 /* Bit 7 (Rx): No response error */
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#define CHNL_ERR_OVERRUN 0x40 /* Bit 6 (Rx): Overrun error */
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#define CHNL_ERR_FRAME 0x80 /* Bit 7 (Tx): Frame error */
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#define CHNL_ERR_COLLISION 0x40 /* Bit 6 (Tx): Collision error */
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#define CHNL_ERR_MASK 0xC0 /* Bit 6-7: channel errors */
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#define IO_READ(addr) (*(vu32*)PHYS_TO_K1(addr))
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#define IO_WRITE(addr,data) (*(vu32*)PHYS_TO_K1(addr)=(u32)(data))
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#endif
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