Decompile osSpTaskLoad
This commit is contained in:
Ryan Dwyer
parent
74f3fe181a
commit
98907a5d07
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@ -0,0 +1,453 @@
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/**************************************************************************
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* *
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* Copyright (C) 1995, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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/**************************************************************************
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*
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* $Revision: 1.13 $
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* $Date: 1997/02/11 08:15:34 $
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* $Source: /disk6/Master/cvsmdev2/PR/include/R4300.h,v $
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*
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**************************************************************************/
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#ifndef __R4300_H__
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#define __R4300_H__
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#include <PR/ultratypes.h>
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/*
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* Segment base addresses and sizes
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*/
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#define KUBASE 0
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#define KUSIZE 0x80000000
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#define K0BASE 0x80000000
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#define K0SIZE 0x20000000
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#define K1BASE 0xA0000000
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#define K1SIZE 0x20000000
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#define K2BASE 0xC0000000
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#define K2SIZE 0x20000000
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/*
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* Exception vectors
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*/
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#define SIZE_EXCVEC 0x80 /* Size of an exc. vec */
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#define UT_VEC K0BASE /* utlbmiss vector */
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#define R_VEC (K1BASE+0x1fc00000) /* reset vector */
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#define XUT_VEC (K0BASE+0x80) /* extended address tlbmiss */
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#define ECC_VEC (K0BASE+0x100) /* Ecc exception vector */
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#define E_VEC (K0BASE+0x180) /* Gen. exception vector */
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/*
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* Address conversion macros
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*/
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#ifdef _LANGUAGE_ASSEMBLY
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#define K0_TO_K1(x) ((x)|0xA0000000) /* kseg0 to kseg1 */
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#define K1_TO_K0(x) ((x)&0x9FFFFFFF) /* kseg1 to kseg0 */
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#define K0_TO_PHYS(x) ((x)&0x1FFFFFFF) /* kseg0 to physical */
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#define K1_TO_PHYS(x) ((x)&0x1FFFFFFF) /* kseg1 to physical */
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#define KDM_TO_PHYS(x) ((x)&0x1FFFFFFF) /* direct mapped to physical */
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#define PHYS_TO_K0(x) ((x)|0x80000000) /* physical to kseg0 */
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#define PHYS_TO_K1(x) ((x)|0xA0000000) /* physical to kseg1 */
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#else /* _LANGUAGE_C */
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#define K0_TO_K1(x) ((u32)(x)|0xA0000000) /* kseg0 to kseg1 */
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#define K1_TO_K0(x) ((u32)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */
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#define K0_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg0 to physical */
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#define K1_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg1 to physical */
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#define KDM_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* direct mapped to physical */
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#define PHYS_TO_K0(x) ((u32)(x)|0x80000000) /* physical to kseg0 */
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#define PHYS_TO_K1(x) ((u32)(x)|0xA0000000) /* physical to kseg1 */
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#endif /* _LANGUAGE_ASSEMBLY */
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/*
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* Address predicates
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*/
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#define IS_KSEG0(x) ((u32)(x) >= K0BASE && (u32)(x) < K1BASE)
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#define IS_KSEG1(x) ((u32)(x) >= K1BASE && (u32)(x) < K2BASE)
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#define IS_KSEGDM(x) ((u32)(x) >= K0BASE && (u32)(x) < K2BASE)
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#define IS_KSEG2(x) ((u32)(x) >= K2BASE && (u32)(x) < KPTE_SHDUBASE)
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#define IS_KPTESEG(x) ((u32)(x) >= KPTE_SHDUBASE)
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#define IS_KUSEG(x) ((u32)(x) < K0BASE)
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/*
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* TLB size constants
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*/
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#define NTLBENTRIES 31 /* entry 31 is reserved by rdb */
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#define TLBHI_VPN2MASK 0xffffe000
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#define TLBHI_VPN2SHIFT 13
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#define TLBHI_PIDMASK 0xff
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#define TLBHI_PIDSHIFT 0
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#define TLBHI_NPID 255 /* 255 to fit in 8 bits */
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#define TLBLO_PFNMASK 0x3fffffc0
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#define TLBLO_PFNSHIFT 6
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#define TLBLO_CACHMASK 0x38 /* cache coherency algorithm */
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#define TLBLO_CACHSHIFT 3
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#define TLBLO_UNCACHED 0x10 /* not cached */
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#define TLBLO_NONCOHRNT 0x18 /* Cacheable non-coherent */
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#define TLBLO_EXLWR 0x28 /* Exclusive write */
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#define TLBLO_D 0x4 /* writeable */
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#define TLBLO_V 0x2 /* valid bit */
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#define TLBLO_G 0x1 /* global access bit */
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#define TLBINX_PROBE 0x80000000
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#define TLBINX_INXMASK 0x3f
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#define TLBINX_INXSHIFT 0
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#define TLBRAND_RANDMASK 0x3f
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#define TLBRAND_RANDSHIFT 0
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#define TLBWIRED_WIREDMASK 0x3f
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#define TLBCTXT_BASEMASK 0xff800000
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#define TLBCTXT_BASESHIFT 23
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#define TLBCTXT_BASEBITS 9
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#define TLBCTXT_VPNMASK 0x7ffff0
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#define TLBCTXT_VPNSHIFT 4
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#define TLBPGMASK_4K 0x0
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#define TLBPGMASK_16K 0x6000
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#define TLBPGMASK_64K 0x1e000
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/*
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* Status register
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*/
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#define SR_CUMASK 0xf0000000 /* coproc usable bits */
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#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
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#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
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#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
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#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
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#define SR_RP 0x08000000 /* Reduced power (quarter speed) */
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#define SR_FR 0x04000000 /* MIPS III FP register mode */
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#define SR_RE 0x02000000 /* Reverse endian */
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#define SR_ITS 0x01000000 /* Instruction trace support */
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#define SR_BEV 0x00400000 /* Use boot exception vectors */
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#define SR_TS 0x00200000 /* TLB shutdown */
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#define SR_SR 0x00100000 /* Soft reset occured */
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#define SR_CH 0x00040000 /* Cache hit for last 'cache' op */
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#define SR_CE 0x00020000 /* Create ECC */
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#define SR_DE 0x00010000 /* ECC of parity does not cause error */
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/*
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* Interrupt enable bits
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* (NOTE: bits set to 1 enable the corresponding level interrupt)
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*/
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#define SR_IMASK 0x0000ff00 /* Interrupt mask */
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#define SR_IMASK8 0x00000000 /* mask level 8 */
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#define SR_IMASK7 0x00008000 /* mask level 7 */
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#define SR_IMASK6 0x0000c000 /* mask level 6 */
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#define SR_IMASK5 0x0000e000 /* mask level 5 */
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#define SR_IMASK4 0x0000f000 /* mask level 4 */
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#define SR_IMASK3 0x0000f800 /* mask level 3 */
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#define SR_IMASK2 0x0000fc00 /* mask level 2 */
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#define SR_IMASK1 0x0000fe00 /* mask level 1 */
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#define SR_IMASK0 0x0000ff00 /* mask level 0 */
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#define SR_IBIT8 0x00008000 /* bit level 8 */
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#define SR_IBIT7 0x00004000 /* bit level 7 */
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#define SR_IBIT6 0x00002000 /* bit level 6 */
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#define SR_IBIT5 0x00001000 /* bit level 5 */
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#define SR_IBIT4 0x00000800 /* bit level 4 */
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#define SR_IBIT3 0x00000400 /* bit level 3 */
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#define SR_IBIT2 0x00000200 /* bit level 2 */
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#define SR_IBIT1 0x00000100 /* bit level 1 */
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#define SR_IMASKSHIFT 8
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#define SR_KX 0x00000080 /* extended-addr TLB vec in kernel */
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#define SR_SX 0x00000040 /* xtended-addr TLB vec supervisor */
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#define SR_UX 0x00000020 /* xtended-addr TLB vec in user mode */
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#define SR_KSU_MASK 0x00000018 /* mode mask */
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#define SR_KSU_USR 0x00000010 /* user mode */
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#define SR_KSU_SUP 0x00000008 /* supervisor mode */
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#define SR_KSU_KER 0x00000000 /* kernel mode */
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#define SR_ERL 0x00000004 /* Error level, 1=>cache error */
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#define SR_EXL 0x00000002 /* Exception level, 1=>exception */
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#define SR_IE 0x00000001 /* interrupt enable, 1=>enable */
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/*
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* Cause Register
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*/
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#define CAUSE_BD 0x80000000 /* Branch delay slot */
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#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
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#define CAUSE_CESHIFT 28
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/* Interrupt pending bits */
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#define CAUSE_IP8 0x00008000 /* External level 8 pending - COMPARE */
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#define CAUSE_IP7 0x00004000 /* External level 7 pending - INT4 */
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#define CAUSE_IP6 0x00002000 /* External level 6 pending - INT3 */
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#define CAUSE_IP5 0x00001000 /* External level 5 pending - INT2 */
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#define CAUSE_IP4 0x00000800 /* External level 4 pending - INT1 */
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#define CAUSE_IP3 0x00000400 /* External level 3 pending - INT0 */
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#define CAUSE_SW2 0x00000200 /* Software level 2 pending */
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#define CAUSE_SW1 0x00000100 /* Software level 1 pending */
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#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */
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#define CAUSE_IPSHIFT 8
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#define CAUSE_EXCMASK 0x0000007C /* Cause code bits */
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#define CAUSE_EXCSHIFT 2
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/* Cause register exception codes */
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#define EXC_CODE(x) ((x)<<2)
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/* Hardware exception codes */
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#define EXC_INT EXC_CODE(0) /* interrupt */
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#define EXC_MOD EXC_CODE(1) /* TLB mod */
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#define EXC_RMISS EXC_CODE(2) /* Read TLB Miss */
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#define EXC_WMISS EXC_CODE(3) /* Write TLB Miss */
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#define EXC_RADE EXC_CODE(4) /* Read Address Error */
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#define EXC_WADE EXC_CODE(5) /* Write Address Error */
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#define EXC_IBE EXC_CODE(6) /* Instruction Bus Error */
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#define EXC_DBE EXC_CODE(7) /* Data Bus Error */
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#define EXC_SYSCALL EXC_CODE(8) /* SYSCALL */
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#define EXC_BREAK EXC_CODE(9) /* BREAKpoint */
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#define EXC_II EXC_CODE(10) /* Illegal Instruction */
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#define EXC_CPU EXC_CODE(11) /* CoProcessor Unusable */
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#define EXC_OV EXC_CODE(12) /* OVerflow */
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#define EXC_TRAP EXC_CODE(13) /* Trap exception */
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#define EXC_VCEI EXC_CODE(14) /* Virt. Coherency on Inst. fetch */
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#define EXC_FPE EXC_CODE(15) /* Floating Point Exception */
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#define EXC_WATCH EXC_CODE(23) /* Watchpoint reference */
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#define EXC_VCED EXC_CODE(31) /* Virt. Coherency on data read */
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/* C0_PRID Defines */
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#define C0_IMPMASK 0xff00
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#define C0_IMPSHIFT 8
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#define C0_REVMASK 0xff
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#define C0_MAJREVMASK 0xf0
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#define C0_MAJREVSHIFT 4
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#define C0_MINREVMASK 0xf
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/*
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* Coprocessor 0 operations
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*/
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#define C0_READI 0x1 /* read ITLB entry addressed by C0_INDEX */
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#define C0_WRITEI 0x2 /* write ITLB entry addressed by C0_INDEX */
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#define C0_WRITER 0x6 /* write ITLB entry addressed by C0_RAND */
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#define C0_PROBE 0x8 /* probe for ITLB entry addressed by TLBHI */
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#define C0_RFE 0x10 /* restore for exception */
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/*
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* 'cache' instruction definitions
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*/
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/* Target cache */
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#define CACH_PI 0x0 /* specifies primary inst. cache */
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#define CACH_PD 0x1 /* primary data cache */
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#define CACH_SI 0x2 /* secondary instruction cache */
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#define CACH_SD 0x3 /* secondary data cache */
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/* Cache operations */
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#define C_IINV 0x0 /* index invalidate (inst, 2nd inst) */
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#define C_IWBINV 0x0 /* index writeback inval (d, sd) */
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#define C_ILT 0x4 /* index load tag (all) */
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#define C_IST 0x8 /* index store tag (all) */
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#define C_CDX 0xc /* create dirty exclusive (d, sd) */
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#define C_HINV 0x10 /* hit invalidate (all) */
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#define C_HWBINV 0x14 /* hit writeback inv. (d, sd) */
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#define C_FILL 0x14 /* fill (i) */
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#define C_HWB 0x18 /* hit writeback (i, d, sd) */
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#define C_HSV 0x1c /* hit set virt. (si, sd) */
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/*
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* Cache size definitions
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*/
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#define ICACHE_SIZE 0x4000 /* 16K */
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#define ICACHE_LINESIZE 32 /* 8 words */
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#define ICACHE_LINEMASK (ICACHE_LINESIZE-1)
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#define DCACHE_SIZE 0x2000 /* 8K */
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#define DCACHE_LINESIZE 16 /* 4 words */
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#define DCACHE_LINEMASK (DCACHE_LINESIZE-1)
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/*
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* C0_CONFIG register definitions
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*/
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#define CONFIG_CM 0x80000000 /* 1 == Master-Checker enabled */
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#define CONFIG_EC 0x70000000 /* System Clock ratio */
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#define CONFIG_EC_1_1 0x6 /* System Clock ratio 1 :1 */
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#define CONFIG_EC_3_2 0x7 /* System Clock ratio 1.5 :1 */
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#define CONFIG_EC_2_1 0x0 /* System Clock ratio 2 :1 */
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#define CONFIG_EC_3_1 0x1 /* System Clock ratio 3 :1 */
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#define CONFIG_EP 0x0f000000 /* Transmit Data Pattern */
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#define CONFIG_SB 0x00c00000 /* Secondary cache block size */
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#define CONFIG_SS 0x00200000 /* Split scache: 0 == I&D combined */
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#define CONFIG_SW 0x00100000 /* scache port: 0==128, 1==64 */
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#define CONFIG_EW 0x000c0000 /* System Port width: 0==64, 1==32 */
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#define CONFIG_SC 0x00020000 /* 0 -> 2nd cache present */
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#define CONFIG_SM 0x00010000 /* 0 -> Dirty Shared Coherency enabled*/
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#define CONFIG_BE 0x00008000 /* Endian-ness: 1 --> BE */
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#define CONFIG_EM 0x00004000 /* 1 -> ECC mode, 0 -> parity */
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#define CONFIG_EB 0x00002000 /* Block order:1->sequent,0->subblock */
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#define CONFIG_IC 0x00000e00 /* Primary Icache size */
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#define CONFIG_DC 0x000001c0 /* Primary Dcache size */
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#define CONFIG_IB 0x00000020 /* Icache block size */
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#define CONFIG_DB 0x00000010 /* Dcache block size */
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#define CONFIG_CU 0x00000008 /* Update on Store-conditional */
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#define CONFIG_K0 0x00000007 /* K0SEG Coherency algorithm */
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#define CONFIG_UNCACHED 0x00000002 /* K0 is uncached */
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#define CONFIG_NONCOHRNT 0x00000003
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#define CONFIG_COHRNT_EXLWR 0x00000005
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#define CONFIG_SB_SHFT 22 /* shift SB to bit position 0 */
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#define CONFIG_IC_SHFT 9 /* shift IC to bit position 0 */
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#define CONFIG_DC_SHFT 6 /* shift DC to bit position 0 */
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#define CONFIG_BE_SHFT 15 /* shift BE to bit position 0 */
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/*
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* C0_TAGLO definitions for setting/getting cache states and physaddr bits
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*/
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#define SADDRMASK 0xFFFFE000 /* 31..13 -> scache paddr bits 35..17 */
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#define SVINDEXMASK 0x00000380 /* 9..7: prim virt index bits 14..12 */
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#define SSTATEMASK 0x00001c00 /* bits 12..10 hold scache line state */
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#define SINVALID 0x00000000 /* invalid --> 000 == state 0 */
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#define SCLEANEXCL 0x00001000 /* clean exclusive --> 100 == state 4 */
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#define SDIRTYEXCL 0x00001400 /* dirty exclusive --> 101 == state 5 */
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#define SECC_MASK 0x0000007f /* low 7 bits are ecc for the tag */
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#define SADDR_SHIFT 4 /* shift STagLo (31..13) to 35..17 */
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#define PADDRMASK 0xFFFFFF00 /* PTagLo31..8->prim paddr bits35..12 */
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#define PADDR_SHIFT 4 /* roll bits 35..12 down to 31..8 */
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#define PSTATEMASK 0x00C0 /* bits 7..6 hold primary line state */
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#define PINVALID 0x0000 /* invalid --> 000 == state 0 */
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#define PCLEANEXCL 0x0080 /* clean exclusive --> 10 == state 2 */
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#define PDIRTYEXCL 0x00C0 /* dirty exclusive --> 11 == state 3 */
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#define PPARITY_MASK 0x0001 /* low bit is parity bit (even). */
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/*
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* C0_CACHE_ERR definitions.
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*/
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#define CACHERR_ER 0x80000000 /* 0: inst ref, 1: data ref */
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#define CACHERR_EC 0x40000000 /* 0: primary, 1: secondary */
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#define CACHERR_ED 0x20000000 /* 1: data error */
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#define CACHERR_ET 0x10000000 /* 1: tag error */
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#define CACHERR_ES 0x08000000 /* 1: external ref, e.g. snoop*/
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#define CACHERR_EE 0x04000000 /* error on SysAD bus */
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#define CACHERR_EB 0x02000000 /* complicated, see spec. */
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#define CACHERR_EI 0x01000000 /* complicated, see spec. */
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#define CACHERR_SIDX_MASK 0x003ffff8 /* secondary cache index */
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#define CACHERR_PIDX_MASK 0x00000007 /* primary cache index */
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#define CACHERR_PIDX_SHIFT 12 /* bits 2..0 are paddr14..12 */
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/* R4000 family supports hardware watchpoints:
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* C0_WATCHLO:
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* bits 31..3 are bits 31..3 of physaddr to watch
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* bit 2: reserved; must be written as 0.
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* bit 1: when set causes a watchpoint trap on load accesses to paddr.
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* bit 0: when set traps on stores to paddr;
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* C0_WATCHHI
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* bits 31..4 are reserved and must be written as zeros.
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* bits 3..0 are bits 35..32 of the physaddr to watch
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*/
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#define WATCHLO_WTRAP 0x00000001
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#define WATCHLO_RTRAP 0x00000002
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#define WATCHLO_ADDRMASK 0xfffffff8
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#define WATCHLO_VALIDMASK 0xfffffffb
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#define WATCHHI_VALIDMASK 0x0000000f
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/*
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* Coprocessor 0 registers
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*/
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#ifdef _LANGUAGE_ASSEMBLY
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#define C0_INX $0
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#define C0_RAND $1
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#define C0_ENTRYLO0 $2
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#define C0_ENTRYLO1 $3
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#define C0_CONTEXT $4
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#define C0_PAGEMASK $5 /* page mask */
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#define C0_WIRED $6 /* # wired entries in tlb */
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#define C0_BADVADDR $8
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#define C0_COUNT $9 /* free-running counter */
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#define C0_ENTRYHI $10
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#define C0_SR $12
|
||||
#define C0_CAUSE $13
|
||||
#define C0_EPC $14
|
||||
#define C0_PRID $15 /* revision identifier */
|
||||
#define C0_COMPARE $11 /* counter comparison reg. */
|
||||
#define C0_CONFIG $16 /* hardware configuration */
|
||||
#define C0_LLADDR $17 /* load linked address */
|
||||
#define C0_WATCHLO $18 /* watchpoint */
|
||||
#define C0_WATCHHI $19 /* watchpoint */
|
||||
#define C0_ECC $26 /* S-cache ECC and primary parity */
|
||||
#define C0_CACHE_ERR $27 /* cache error status */
|
||||
#define C0_TAGLO $28 /* cache operations */
|
||||
#define C0_TAGHI $29 /* cache operations */
|
||||
#define C0_ERROR_EPC $30 /* ECC error prg. counter */
|
||||
|
||||
# else /* ! _LANGUAGE_ASSEMBLY */
|
||||
|
||||
#define C0_INX 0
|
||||
#define C0_RAND 1
|
||||
#define C0_ENTRYLO0 2
|
||||
#define C0_ENTRYLO1 3
|
||||
#define C0_CONTEXT 4
|
||||
#define C0_PAGEMASK 5 /* page mask */
|
||||
#define C0_WIRED 6 /* # wired entries in tlb */
|
||||
#define C0_BADVADDR 8
|
||||
#define C0_COUNT 9 /* free-running counter */
|
||||
#define C0_ENTRYHI 10
|
||||
#define C0_SR 12
|
||||
#define C0_CAUSE 13
|
||||
#define C0_EPC 14
|
||||
#define C0_PRID 15 /* revision identifier */
|
||||
#define C0_COMPARE 11 /* counter comparison reg. */
|
||||
#define C0_CONFIG 16 /* hardware configuration */
|
||||
#define C0_LLADDR 17 /* load linked address */
|
||||
#define C0_WATCHLO 18 /* watchpoint */
|
||||
#define C0_WATCHHI 19 /* watchpoint */
|
||||
#define C0_ECC 26 /* S-cache ECC and primary parity */
|
||||
#define C0_CACHE_ERR 27 /* cache error status */
|
||||
#define C0_TAGLO 28 /* cache operations */
|
||||
#define C0_TAGHI 29 /* cache operations */
|
||||
#define C0_ERROR_EPC 30 /* ECC error prg. counter */
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
/*
|
||||
* floating-point status register
|
||||
*/
|
||||
#define FPCSR_FS 0x01000000 /* flush denorm to zero */
|
||||
#define FPCSR_C 0x00800000 /* condition bit */
|
||||
#define FPCSR_CE 0x00020000 /* cause: unimplemented operation */
|
||||
#define FPCSR_CV 0x00010000 /* cause: invalid operation */
|
||||
#define FPCSR_CZ 0x00008000 /* cause: division by zero */
|
||||
#define FPCSR_CO 0x00004000 /* cause: overflow */
|
||||
#define FPCSR_CU 0x00002000 /* cause: underflow */
|
||||
#define FPCSR_CI 0x00001000 /* cause: inexact operation */
|
||||
#define FPCSR_EV 0x00000800 /* enable: invalid operation */
|
||||
#define FPCSR_EZ 0x00000400 /* enable: division by zero */
|
||||
#define FPCSR_EO 0x00000200 /* enable: overflow */
|
||||
#define FPCSR_EU 0x00000100 /* enable: underflow */
|
||||
#define FPCSR_EI 0x00000080 /* enable: inexact operation */
|
||||
#define FPCSR_FV 0x00000040 /* flag: invalid operation */
|
||||
#define FPCSR_FZ 0x00000020 /* flag: division by zero */
|
||||
#define FPCSR_FO 0x00000010 /* flag: overflow */
|
||||
#define FPCSR_FU 0x00000008 /* flag: underflow */
|
||||
#define FPCSR_FI 0x00000004 /* flag: inexact operation */
|
||||
#define FPCSR_RM_MASK 0x00000003 /* rounding mode mask */
|
||||
#define FPCSR_RM_RN 0x00000000 /* round to nearest */
|
||||
#define FPCSR_RM_RZ 0x00000001 /* round to zero */
|
||||
#define FPCSR_RM_RP 0x00000002 /* round to positive infinity */
|
||||
#define FPCSR_RM_RM 0x00000003 /* round to negative infinity */
|
||||
|
||||
#endif /* __R4300_H */
|
||||
|
|
@ -0,0 +1,882 @@
|
|||
#ifndef _RCP_H_
|
||||
#define _RCP_H_
|
||||
|
||||
/**************************************************************************
|
||||
* *
|
||||
* Copyright (C) 1995, Silicon Graphics, Inc. *
|
||||
* *
|
||||
* These coded instructions, statements, and computer programs contain *
|
||||
* unpublished proprietary information of Silicon Graphics, Inc., and *
|
||||
* are protected by Federal copyright law. They may not be disclosed *
|
||||
* to third parties or copied or duplicated in any form, in whole or *
|
||||
* in part, without the prior written consent of Silicon Graphics, Inc. *
|
||||
* *
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* File: rcp.h
|
||||
*
|
||||
* This file contains register and bit definitions for RCP memory map.
|
||||
* $Revision: 1.20 $
|
||||
* $Date: 1997/07/23 08:35:21 $
|
||||
* $Source: /disk6/Master/cvsmdev2/PR/include/rcp.h,v $
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#include <PR/R4300.h>
|
||||
#include <PR/ultratypes.h>
|
||||
|
||||
/**********************************************************************
|
||||
*
|
||||
* Here is a quick overview of the RCP memory map:
|
||||
*
|
||||
|
||||
0x0000_0000 .. 0x03ef_ffff RDRAM memory
|
||||
0x03f0_0000 .. 0x03ff_ffff RDRAM registers
|
||||
|
||||
RCP registers (see below)
|
||||
0x0400_0000 .. 0x040f_ffff SP registers
|
||||
0x0410_0000 .. 0x041f_ffff DP command registers
|
||||
0x0420_0000 .. 0x042f_ffff DP span registers
|
||||
0x0430_0000 .. 0x043f_ffff MI registers
|
||||
0x0440_0000 .. 0x044f_ffff VI registers
|
||||
0x0450_0000 .. 0x045f_ffff AI registers
|
||||
0x0460_0000 .. 0x046f_ffff PI registers
|
||||
0x0470_0000 .. 0x047f_ffff RI registers
|
||||
0x0480_0000 .. 0x048f_ffff SI registers
|
||||
0x0490_0000 .. 0x04ff_ffff unused
|
||||
|
||||
0x0500_0000 .. 0x05ff_ffff cartridge domain 2
|
||||
0x0600_0000 .. 0x07ff_ffff cartridge domain 1
|
||||
0x0800_0000 .. 0x0fff_ffff cartridge domain 2
|
||||
0x1000_0000 .. 0x1fbf_ffff cartridge domain 1
|
||||
|
||||
0x1fc0_0000 .. 0x1fc0_07bf PIF Boot Rom (1984 bytes)
|
||||
0x1fc0_07c0 .. 0x1fc0_07ff PIF (JoyChannel) RAM (64 bytes)
|
||||
0x1fc0_0800 .. 0x1fcf_ffff Reserved
|
||||
0x1fd0_0000 .. 0x7fff_ffff cartridge domain 1
|
||||
0x8000_0000 .. 0xffff_ffff external SysAD device
|
||||
|
||||
The Indy development board use cartridge domain 1:
|
||||
0x1000_0000 .. 0x10ff_ffff RAMROM
|
||||
0x1800_0000 .. 0x1800_0003 GIO interrupt (6 bits valid in 4 bytes)
|
||||
0x1800_0400 .. 0x1800_0403 GIO sync (6 bits valid in 4 bytes)
|
||||
0x1800_0800 .. 0x1800_0803 CART interrupt (6 bits valid in 4 bytes)
|
||||
|
||||
|
||||
|
||||
**************************************************************************/
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* RDRAM Memory (Assumes that maximum size is 4 MB)
|
||||
*/
|
||||
#define RDRAM_0_START 0x00000000
|
||||
#define RDRAM_0_END 0x001FFFFF
|
||||
#define RDRAM_1_START 0x00200000
|
||||
#define RDRAM_1_END 0x003FFFFF
|
||||
|
||||
#define RDRAM_START RDRAM_0_START
|
||||
#define RDRAM_END RDRAM_1_END
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Address predicates
|
||||
*/
|
||||
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
|
||||
#define IS_RDRAM(x) ((unsigned)(x) >= RDRAM_START && \
|
||||
(unsigned)(x) < RDRAM_END)
|
||||
#endif
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* RDRAM Registers (0x03f0_0000 .. 0x03ff_ffff)
|
||||
*/
|
||||
#define RDRAM_BASE_REG 0x03F00000
|
||||
|
||||
#define RDRAM_CONFIG_REG (RDRAM_BASE_REG+0x00)
|
||||
#define RDRAM_DEVICE_TYPE_REG (RDRAM_BASE_REG+0x00)
|
||||
#define RDRAM_DEVICE_ID_REG (RDRAM_BASE_REG+0x04)
|
||||
#define RDRAM_DELAY_REG (RDRAM_BASE_REG+0x08)
|
||||
#define RDRAM_MODE_REG (RDRAM_BASE_REG+0x0c)
|
||||
#define RDRAM_REF_INTERVAL_REG (RDRAM_BASE_REG+0x10)
|
||||
#define RDRAM_REF_ROW_REG (RDRAM_BASE_REG+0x14)
|
||||
#define RDRAM_RAS_INTERVAL_REG (RDRAM_BASE_REG+0x18)
|
||||
#define RDRAM_MIN_INTERVAL_REG (RDRAM_BASE_REG+0x1c)
|
||||
#define RDRAM_ADDR_SELECT_REG (RDRAM_BASE_REG+0x20)
|
||||
#define RDRAM_DEVICE_MANUF_REG (RDRAM_BASE_REG+0x24)
|
||||
|
||||
#define RDRAM_0_DEVICE_ID 0
|
||||
#define RDRAM_1_DEVICE_ID 1
|
||||
|
||||
#define RDRAM_RESET_MODE 0
|
||||
#define RDRAM_ACTIVE_MODE 1
|
||||
#define RDRAM_STANDBY_MODE 2
|
||||
|
||||
#define RDRAM_LENGTH (2*512*2048)
|
||||
#define RDRAM_0_BASE_ADDRESS (RDRAM_0_DEVICE_ID*RDRAM_LENGTH)
|
||||
#define RDRAM_1_BASE_ADDRESS (RDRAM_1_DEVICE_ID*RDRAM_LENGTH)
|
||||
|
||||
#define RDRAM_0_CONFIG 0x00000
|
||||
#define RDRAM_1_CONFIG 0x00400
|
||||
#define RDRAM_GLOBAL_CONFIG 0x80000
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* PIF Physical memory map (total size = 2 KB)
|
||||
*
|
||||
* Size Description Mode
|
||||
* 1FC007FF +-------+-----------------+-----+
|
||||
* | 64 B | JoyChannel RAM | R/W |
|
||||
* 1FC007C0 +-------+-----------------+-----+
|
||||
* |1984 B | Boot ROM | * | * = Reserved
|
||||
* 1FC00000 +-------+-----------------+-----+
|
||||
*
|
||||
*/
|
||||
#define PIF_ROM_START 0x1FC00000
|
||||
#define PIF_ROM_END 0x1FC007BF
|
||||
#define PIF_RAM_START 0x1FC007C0
|
||||
#define PIF_RAM_END 0x1FC007FF
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Controller channel
|
||||
* Each game controller channel has 4 error bits that are defined in bit 6-7 of
|
||||
* the Rx and Tx data size area bytes. Programmers need to clear these bits
|
||||
* when setting the Tx/Rx size area values for a channel
|
||||
*/
|
||||
#define CHNL_ERR_NORESP 0x80 /* Bit 7 (Rx): No response error */
|
||||
#define CHNL_ERR_OVERRUN 0x40 /* Bit 6 (Rx): Overrun error */
|
||||
#define CHNL_ERR_FRAME 0x80 /* Bit 7 (Tx): Frame error */
|
||||
#define CHNL_ERR_COLLISION 0x40 /* Bit 6 (Tx): Collision error */
|
||||
|
||||
#define CHNL_ERR_MASK 0xC0 /* Bit 6-7: channel errors */
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* External device info
|
||||
*/
|
||||
#define DEVICE_TYPE_CART 0 /* ROM cartridge */
|
||||
#define DEVICE_TYPE_BULK 1 /* ROM bulk */
|
||||
#define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */
|
||||
#define DEVICE_TYPE_SRAM 3 /* SRAM */
|
||||
|
||||
/*************************************************************************
|
||||
* SP Memory
|
||||
*/
|
||||
#define SP_DMEM_START 0x04000000 /* read/write */
|
||||
#define SP_DMEM_END 0x04000FFF
|
||||
#define SP_IMEM_START 0x04001000 /* read/write */
|
||||
#define SP_IMEM_END 0x04001FFF
|
||||
|
||||
/*************************************************************************
|
||||
* SP CP0 Registers
|
||||
*/
|
||||
|
||||
#define SP_BASE_REG 0x04040000
|
||||
|
||||
/* SP memory address (R/W): [11:0] DMEM/IMEM address; [12] 0=DMEM,1=IMEM */
|
||||
#define SP_MEM_ADDR_REG (SP_BASE_REG+0x00) /* Master */
|
||||
|
||||
/* SP DRAM DMA address (R/W): [23:0] RDRAM address */
|
||||
#define SP_DRAM_ADDR_REG (SP_BASE_REG+0x04) /* Slave */
|
||||
|
||||
/* SP read DMA length (R/W): [11:0] length, [19:12] count, [31:20] skip */
|
||||
/* direction: I/DMEM <- RDRAM */
|
||||
#define SP_RD_LEN_REG (SP_BASE_REG+0x08) /* R/W: read len */
|
||||
|
||||
/* SP write DMA length (R/W): [11:0] length, [19:12] count, [31:20] skip */
|
||||
/* direction: I/DMEM -> RDRAM */
|
||||
#define SP_WR_LEN_REG (SP_BASE_REG+0x0C) /* R/W: write len */
|
||||
|
||||
/* SP status (R/W): [14:0] valid bits; see below for write/read mode */
|
||||
#define SP_STATUS_REG (SP_BASE_REG+0x10)
|
||||
|
||||
/* SP DMA full (R): [0] valid bit; dma full */
|
||||
#define SP_DMA_FULL_REG (SP_BASE_REG+0x14)
|
||||
|
||||
/* SP DMA busy (R): [0] valid bit; dma busy */
|
||||
#define SP_DMA_BUSY_REG (SP_BASE_REG+0x18)
|
||||
|
||||
/* SP semaphore (R/W): Read: [0] semaphore flag (set on read) */
|
||||
/* Write: [] clear semaphore flag */
|
||||
#define SP_SEMAPHORE_REG (SP_BASE_REG+0x1C)
|
||||
|
||||
/* SP PC (R/W): [11:0] program counter */
|
||||
#define SP_PC_REG 0x04080000
|
||||
|
||||
/* SP MEM address: bit 12 specifies if address is IMEM or DMEM */
|
||||
#define SP_DMA_DMEM 0x0000 /* Bit 12: 0=DMEM, 1=IMEM */
|
||||
#define SP_DMA_IMEM 0x1000 /* Bit 12: 0=DMEM, 1=IMEM */
|
||||
|
||||
/*
|
||||
* Values to clear/set bit in status reg (SP_STATUS_REG - write)
|
||||
*/
|
||||
#define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */
|
||||
#define SP_SET_HALT 0x00002 /* Bit 1: set halt */
|
||||
#define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */
|
||||
#define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */
|
||||
#define SP_SET_INTR 0x00010 /* Bit 4: set intr */
|
||||
#define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */
|
||||
#define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */
|
||||
#define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */
|
||||
#define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */
|
||||
#define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */
|
||||
#define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */
|
||||
#define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */
|
||||
#define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */
|
||||
#define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */
|
||||
#define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */
|
||||
#define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */
|
||||
#define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */
|
||||
#define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */
|
||||
#define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */
|
||||
#define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */
|
||||
#define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */
|
||||
#define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */
|
||||
#define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */
|
||||
#define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */
|
||||
#define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */
|
||||
|
||||
/*
|
||||
* Patterns to interpret status reg (SP_STATUS_REG - read)
|
||||
*/
|
||||
#define SP_STATUS_HALT 0x001 /* Bit 0: halt */
|
||||
#define SP_STATUS_BROKE 0x002 /* Bit 1: broke */
|
||||
#define SP_STATUS_DMA_BUSY 0x004 /* Bit 2: dma busy */
|
||||
#define SP_STATUS_DMA_FULL 0x008 /* Bit 3: dma full */
|
||||
#define SP_STATUS_IO_FULL 0x010 /* Bit 4: io full */
|
||||
#define SP_STATUS_SSTEP 0x020 /* Bit 5: single step */
|
||||
#define SP_STATUS_INTR_BREAK 0x040 /* Bit 6: interrupt on break */
|
||||
#define SP_STATUS_SIG0 0x080 /* Bit 7: signal 0 set */
|
||||
#define SP_STATUS_SIG1 0x100 /* Bit 8: signal 1 set */
|
||||
#define SP_STATUS_SIG2 0x200 /* Bit 9: signal 2 set */
|
||||
#define SP_STATUS_SIG3 0x400 /* Bit 10: signal 3 set */
|
||||
#define SP_STATUS_SIG4 0x800 /* Bit 11: signal 4 set */
|
||||
#define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */
|
||||
#define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */
|
||||
#define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */
|
||||
|
||||
/*
|
||||
* Use of SIG bits
|
||||
*/
|
||||
#define SP_CLR_YIELD SP_CLR_SIG0
|
||||
#define SP_SET_YIELD SP_SET_SIG0
|
||||
#define SP_STATUS_YIELD SP_STATUS_SIG0
|
||||
#define SP_CLR_YIELDED SP_CLR_SIG1
|
||||
#define SP_SET_YIELDED SP_SET_SIG1
|
||||
#define SP_STATUS_YIELDED SP_STATUS_SIG1
|
||||
#define SP_CLR_TASKDONE SP_CLR_SIG2
|
||||
#define SP_SET_TASKDONE SP_SET_SIG2
|
||||
#define SP_STATUS_TASKDONE SP_STATUS_SIG2
|
||||
#define SP_CLR_RSPSIGNAL SP_CLR_SIG3
|
||||
#define SP_SET_RSPSIGNAL SP_SET_SIG3
|
||||
#define SP_STATUS_RSPSIGNAL SP_STATUS_SIG3
|
||||
#define SP_CLR_CPUSIGNAL SP_CLR_SIG4
|
||||
#define SP_SET_CPUSIGNAL SP_SET_SIG4
|
||||
#define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4
|
||||
|
||||
/* SP IMEM BIST REG (R/W): [6:0] BIST status bits; see below for detail */
|
||||
#define SP_IBIST_REG 0x04080004
|
||||
|
||||
/*
|
||||
* Patterns to interpret status reg (SP_BIST_REG - write)
|
||||
*/
|
||||
#define SP_IBIST_CHECK 0x01 /* Bit 0: BIST check */
|
||||
#define SP_IBIST_GO 0x02 /* Bit 1: BIST go */
|
||||
#define SP_IBIST_CLEAR 0x04 /* Bit 2: BIST clear */
|
||||
|
||||
/*
|
||||
* Patterns to interpret status reg (SP_BIST_REG - read)
|
||||
*/
|
||||
/* First 2 bits are same as in write mode:
|
||||
* Bit 0: BIST check; Bit 1: BIST go
|
||||
*/
|
||||
#define SP_IBIST_DONE 0x04 /* Bit 2: BIST done */
|
||||
#define SP_IBIST_FAILED 0x78 /* Bit [6:3]: BIST fail */
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* DP Command Registers
|
||||
*/
|
||||
#define DPC_BASE_REG 0x04100000
|
||||
|
||||
/* DP CMD DMA start (R/W): [23:0] DMEM/RDRAM start address */
|
||||
#define DPC_START_REG (DPC_BASE_REG+0x00)
|
||||
|
||||
/* DP CMD DMA end (R/W): [23:0] DMEM/RDRAM end address */
|
||||
#define DPC_END_REG (DPC_BASE_REG+0x04)
|
||||
|
||||
/* DP CMD DMA end (R): [23:0] DMEM/RDRAM current address */
|
||||
#define DPC_CURRENT_REG (DPC_BASE_REG+0x08)
|
||||
|
||||
/* DP CMD status (R/W): [9:0] valid bits - see below for definitions */
|
||||
#define DPC_STATUS_REG (DPC_BASE_REG+0x0C)
|
||||
|
||||
/* DP clock counter (R): [23:0] clock counter */
|
||||
#define DPC_CLOCK_REG (DPC_BASE_REG+0x10)
|
||||
|
||||
/* DP buffer busy counter (R): [23:0] clock counter */
|
||||
#define DPC_BUFBUSY_REG (DPC_BASE_REG+0x14)
|
||||
|
||||
/* DP pipe busy counter (R): [23:0] clock counter */
|
||||
#define DPC_PIPEBUSY_REG (DPC_BASE_REG+0x18)
|
||||
|
||||
/* DP TMEM load counter (R): [23:0] clock counter */
|
||||
#define DPC_TMEM_REG (DPC_BASE_REG+0x1C)
|
||||
|
||||
/*
|
||||
* Values to clear/set bit in status reg (DPC_STATUS_REG - write)
|
||||
*/
|
||||
#define DPC_CLR_XBUS_DMEM_DMA 0x0001 /* Bit 0: clear xbus_dmem_dma */
|
||||
#define DPC_SET_XBUS_DMEM_DMA 0x0002 /* Bit 1: set xbus_dmem_dma */
|
||||
#define DPC_CLR_FREEZE 0x0004 /* Bit 2: clear freeze */
|
||||
#define DPC_SET_FREEZE 0x0008 /* Bit 3: set freeze */
|
||||
#define DPC_CLR_FLUSH 0x0010 /* Bit 4: clear flush */
|
||||
#define DPC_SET_FLUSH 0x0020 /* Bit 5: set flush */
|
||||
#define DPC_CLR_TMEM_CTR 0x0040 /* Bit 6: clear tmem ctr */
|
||||
#define DPC_CLR_PIPE_CTR 0x0080 /* Bit 7: clear pipe ctr */
|
||||
#define DPC_CLR_CMD_CTR 0x0100 /* Bit 8: clear cmd ctr */
|
||||
#define DPC_CLR_CLOCK_CTR 0x0200 /* Bit 9: clear clock ctr */
|
||||
|
||||
/*
|
||||
* Patterns to interpret status reg (DPC_STATUS_REG - read)
|
||||
*/
|
||||
#define DPC_STATUS_XBUS_DMEM_DMA 0x001 /* Bit 0: xbus_dmem_dma */
|
||||
#define DPC_STATUS_FREEZE 0x002 /* Bit 1: freeze */
|
||||
#define DPC_STATUS_FLUSH 0x004 /* Bit 2: flush */
|
||||
/*#define DPC_STATUS_FROZEN 0x008*/ /* Bit 3: frozen */
|
||||
#define DPC_STATUS_START_GCLK 0x008 /* Bit 3: start gclk */
|
||||
#define DPC_STATUS_TMEM_BUSY 0x010 /* Bit 4: tmem busy */
|
||||
#define DPC_STATUS_PIPE_BUSY 0x020 /* Bit 5: pipe busy */
|
||||
#define DPC_STATUS_CMD_BUSY 0x040 /* Bit 6: cmd busy */
|
||||
#define DPC_STATUS_CBUF_READY 0x080 /* Bit 7: cbuf ready */
|
||||
#define DPC_STATUS_DMA_BUSY 0x100 /* Bit 8: dma busy */
|
||||
#define DPC_STATUS_END_VALID 0x200 /* Bit 9: end valid */
|
||||
#define DPC_STATUS_START_VALID 0x400 /* Bit 10: start valid */
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* DP Span Registers
|
||||
*/
|
||||
#define DPS_BASE_REG 0x04200000
|
||||
|
||||
/* DP tmem bist (R/W): [10:0] BIST status bits; see below for detail */
|
||||
#define DPS_TBIST_REG (DPS_BASE_REG+0x00)
|
||||
|
||||
/* DP span test mode (R/W): [0] Span buffer test access enable */
|
||||
#define DPS_TEST_MODE_REG (DPS_BASE_REG+0x04)
|
||||
|
||||
/* DP span buffer test address (R/W): [6:0] bits; see below for detail */
|
||||
#define DPS_BUFTEST_ADDR_REG (DPS_BASE_REG+0x08)
|
||||
|
||||
/* DP span buffer test data (R/W): [31:0] span buffer data */
|
||||
#define DPS_BUFTEST_DATA_REG (DPS_BASE_REG+0x0C)
|
||||
|
||||
/*
|
||||
* Patterns to interpret status reg (DPS_TMEM_BIST_REG - write)
|
||||
*/
|
||||
#define DPS_TBIST_CHECK 0x01 /* Bit 0: BIST check */
|
||||
#define DPS_TBIST_GO 0x02 /* Bit 1: BIST go */
|
||||
#define DPS_TBIST_CLEAR 0x04 /* Bit 2: BIST clear */
|
||||
|
||||
/*
|
||||
* Patterns to interpret status reg (DPS_TMEM_BIST_REG - read)
|
||||
*/
|
||||
/* First 2 bits are same as in write mode:
|
||||
* Bit 0: BIST check; Bit 1: BIST go
|
||||
*/
|
||||
#define DPS_TBIST_DONE 0x004 /* Bit 2: BIST done */
|
||||
#define DPS_TBIST_FAILED 0x7F8 /* Bit [10:3]: BIST fail */
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* MIPS Interface (MI) Registers
|
||||
*/
|
||||
#define MI_BASE_REG 0x04300000
|
||||
|
||||
/*
|
||||
* MI init mode (W): [6:0] init length, [7] clear init mode, [8] set init mode
|
||||
* [9/10] clear/set ebus test mode, [11] clear DP interrupt
|
||||
* (R): [6:0] init length, [7] init mode, [8] ebus test mode
|
||||
*/
|
||||
#define MI_INIT_MODE_REG (MI_BASE_REG+0x00)
|
||||
#define MI_MODE_REG MI_INIT_MODE_REG
|
||||
|
||||
/*
|
||||
* Values to clear/set bit in mode reg (MI_MODE_REG - write)
|
||||
*/
|
||||
#define MI_CLR_INIT 0x0080 /* Bit 7: clear init mode */
|
||||
#define MI_SET_INIT 0x0100 /* Bit 8: set init mode */
|
||||
#define MI_CLR_EBUS 0x0200 /* Bit 9: clear ebus test */
|
||||
#define MI_SET_EBUS 0x0400 /* Bit 10: set ebus test mode */
|
||||
#define MI_CLR_DP_INTR 0x0800 /* Bit 11: clear dp interrupt */
|
||||
#define MI_CLR_RDRAM 0x1000 /* Bit 12: clear RDRAM reg */
|
||||
#define MI_SET_RDRAM 0x2000 /* Bit 13: set RDRAM reg mode */
|
||||
|
||||
/*
|
||||
* Patterns to interpret mode reg (MI_MODE_REG - read)
|
||||
*/
|
||||
#define MI_MODE_INIT 0x0080 /* Bit 7: init mode */
|
||||
#define MI_MODE_EBUS 0x0100 /* Bit 8: ebus test mode */
|
||||
#define MI_MODE_RDRAM 0x0200 /* Bit 9: RDRAM reg mode */
|
||||
|
||||
/* MI version (R): [7:0] io, [15:8] rac, [23:16] rdp, [31:24] rsp */
|
||||
#define MI_VERSION_REG (MI_BASE_REG+0x04)
|
||||
#define MI_NOOP_REG MI_VERSION_REG
|
||||
|
||||
/* MI interrupt (R): [5:0] valid bits - see below for bit patterns */
|
||||
#define MI_INTR_REG (MI_BASE_REG+0x08)
|
||||
|
||||
/*
|
||||
* MI interrupt mask (W): [11:0] valid bits - see below for bit patterns
|
||||
* (R): [5:0] valid bits - see below for bit patterns
|
||||
*/
|
||||
#define MI_INTR_MASK_REG (MI_BASE_REG+0x0C)
|
||||
|
||||
/*
|
||||
* The following are values to check for interrupt setting (MI_INTR_REG)
|
||||
*/
|
||||
#define MI_INTR_SP 0x01 /* Bit 0: SP intr */
|
||||
#define MI_INTR_SI 0x02 /* Bit 1: SI intr */
|
||||
#define MI_INTR_AI 0x04 /* Bit 2: AI intr */
|
||||
#define MI_INTR_VI 0x08 /* Bit 3: VI intr */
|
||||
#define MI_INTR_PI 0x10 /* Bit 4: PI intr */
|
||||
#define MI_INTR_DP 0x20 /* Bit 5: DP intr */
|
||||
|
||||
/*
|
||||
* The following are values to clear/set various interrupt bit mask
|
||||
* They can be ORed together to manipulate multiple bits
|
||||
* (MI_INTR_MASK_REG - write)
|
||||
*/
|
||||
#define MI_INTR_MASK_CLR_SP 0x0001 /* Bit 0: clear SP mask */
|
||||
#define MI_INTR_MASK_SET_SP 0x0002 /* Bit 1: set SP mask */
|
||||
#define MI_INTR_MASK_CLR_SI 0x0004 /* Bit 2: clear SI mask */
|
||||
#define MI_INTR_MASK_SET_SI 0x0008 /* Bit 3: set SI mask */
|
||||
#define MI_INTR_MASK_CLR_AI 0x0010 /* Bit 4: clear AI mask */
|
||||
#define MI_INTR_MASK_SET_AI 0x0020 /* Bit 5: set AI mask */
|
||||
#define MI_INTR_MASK_CLR_VI 0x0040 /* Bit 6: clear VI mask */
|
||||
#define MI_INTR_MASK_SET_VI 0x0080 /* Bit 7: set VI mask */
|
||||
#define MI_INTR_MASK_CLR_PI 0x0100 /* Bit 8: clear PI mask */
|
||||
#define MI_INTR_MASK_SET_PI 0x0200 /* Bit 9: set PI mask */
|
||||
#define MI_INTR_MASK_CLR_DP 0x0400 /* Bit 10: clear DP mask */
|
||||
#define MI_INTR_MASK_SET_DP 0x0800 /* Bit 11: set DP mask */
|
||||
|
||||
/*
|
||||
* The following are values to check for interrupt mask setting
|
||||
* (MI_INTR_MASK_REG - read)
|
||||
*/
|
||||
#define MI_INTR_MASK_SP 0x01 /* Bit 0: SP intr mask */
|
||||
#define MI_INTR_MASK_SI 0x02 /* Bit 1: SI intr mask */
|
||||
#define MI_INTR_MASK_AI 0x04 /* Bit 2: AI intr mask */
|
||||
#define MI_INTR_MASK_VI 0x08 /* Bit 3: VI intr mask */
|
||||
#define MI_INTR_MASK_PI 0x10 /* Bit 4: PI intr mask */
|
||||
#define MI_INTR_MASK_DP 0x20 /* Bit 5: DP intr mask */
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Video Interface (VI) Registers
|
||||
*/
|
||||
#define VI_BASE_REG 0x04400000
|
||||
|
||||
/* VI status/control (R/W): [15-0] valid bits:
|
||||
* [1:0] = type[1:0] (pixel size)
|
||||
* 0: blank (no data, no sync)
|
||||
* 1: reserved
|
||||
* 2: 5/5/5/3 ("16" bit)
|
||||
* 3: 8/8/8/8 (32 bit)
|
||||
* [2] = gamma_dither_enable (normally on, unless "special effect")
|
||||
* [3] = gamma_enable (normally on, unless MPEG/JPEG)
|
||||
* [4] = divot_enable (normally on if antialiased, unless decal lines)
|
||||
* [5] = reserved - always off
|
||||
* [6] = serrate (always on if interlaced, off if not)
|
||||
* [7] = reserved - diagnostics only
|
||||
* [9:8] = anti-alias (aa) mode[1:0]
|
||||
* 0: aa & resamp (always fetch extra lines)
|
||||
* 1: aa & resamp (fetch extra lines if needed)
|
||||
* 2: resamp only (treat as all fully covered)
|
||||
* 3: neither (replicate pixels, no interpolate)
|
||||
* [11] = reserved - diagnostics only
|
||||
* [15:12] = reserved
|
||||
*
|
||||
*/
|
||||
#define VI_STATUS_REG (VI_BASE_REG+0x00)
|
||||
#define VI_CONTROL_REG VI_STATUS_REG
|
||||
|
||||
/* VI origin (R/W): [23:0] frame buffer origin in bytes */
|
||||
#define VI_ORIGIN_REG (VI_BASE_REG+0x04)
|
||||
#define VI_DRAM_ADDR_REG VI_ORIGIN_REG
|
||||
|
||||
/* VI width (R/W): [11:0] frame buffer line width in pixels */
|
||||
#define VI_WIDTH_REG (VI_BASE_REG+0x08)
|
||||
#define VI_H_WIDTH_REG VI_WIDTH_REG
|
||||
|
||||
/* VI vertical intr (R/W): [9:0] interrupt when current half-line = V_INTR */
|
||||
#define VI_INTR_REG (VI_BASE_REG+0x0C)
|
||||
#define VI_V_INTR_REG VI_INTR_REG
|
||||
|
||||
/*
|
||||
* VI current vertical line (R/W): [9:0] current half line, sampled once per
|
||||
* line (the lsb of V_CURRENT is constant within a field, and in
|
||||
* interlaced modes gives the field number - which is constant for non-
|
||||
* interlaced modes)
|
||||
* - Any write to this register will clear interrupt line
|
||||
*/
|
||||
#define VI_CURRENT_REG (VI_BASE_REG+0x10)
|
||||
#define VI_V_CURRENT_LINE_REG VI_CURRENT_REG
|
||||
|
||||
/*
|
||||
* VI video timing (R/W): [ 7: 0] horizontal sync width in pixels,
|
||||
* [15: 8] color burst width in pixels,
|
||||
* [19:16] vertical sync width in half lines,
|
||||
* [29:20] start of color burst in pixels from h-sync
|
||||
*/
|
||||
#define VI_BURST_REG (VI_BASE_REG+0x14)
|
||||
#define VI_TIMING_REG VI_BURST_REG
|
||||
|
||||
/* VI vertical sync (R/W): [9:0] number of half-lines per field */
|
||||
#define VI_V_SYNC_REG (VI_BASE_REG+0x18)
|
||||
|
||||
/* VI horizontal sync (R/W): [11: 0] total duration of a line in 1/4 pixel
|
||||
* [20:16] a 5-bit leap pattern used for PAL only
|
||||
* (h_sync_period)
|
||||
*/
|
||||
#define VI_H_SYNC_REG (VI_BASE_REG+0x1C)
|
||||
|
||||
/*
|
||||
* VI horizontal sync leap (R/W): [11: 0] identical to h_sync_period
|
||||
* [27:16] identical to h_sync_period
|
||||
*/
|
||||
#define VI_LEAP_REG (VI_BASE_REG+0x20)
|
||||
#define VI_H_SYNC_LEAP_REG VI_LEAP_REG
|
||||
|
||||
/*
|
||||
* VI horizontal video (R/W): [ 9: 0] end of active video in screen pixels
|
||||
* : [25:16] start of active video in screen pixels
|
||||
*/
|
||||
#define VI_H_START_REG (VI_BASE_REG+0x24)
|
||||
#define VI_H_VIDEO_REG VI_H_START_REG
|
||||
|
||||
/*
|
||||
* VI vertical video (R/W): [ 9: 0] end of active video in screen half-lines
|
||||
* : [25:16] start of active video in screen half-lines
|
||||
*/
|
||||
#define VI_V_START_REG (VI_BASE_REG+0x28)
|
||||
#define VI_V_VIDEO_REG VI_V_START_REG
|
||||
|
||||
/*
|
||||
* VI vertical burst (R/W): [ 9: 0] end of color burst enable in half-lines
|
||||
* : [25:16] start of color burst enable in half-lines
|
||||
*/
|
||||
#define VI_V_BURST_REG (VI_BASE_REG+0x2C)
|
||||
|
||||
/* VI x-scale (R/W): [11: 0] 1/horizontal scale up factor (2.10 format)
|
||||
* [27:16] horizontal subpixel offset (2.10 format)
|
||||
*/
|
||||
#define VI_X_SCALE_REG (VI_BASE_REG+0x30)
|
||||
|
||||
/* VI y-scale (R/W): [11: 0] 1/vertical scale up factor (2.10 format)
|
||||
* [27:16] vertical subpixel offset (2.10 format)
|
||||
*/
|
||||
#define VI_Y_SCALE_REG (VI_BASE_REG+0x34)
|
||||
|
||||
/*
|
||||
* Patterns to interpret VI_CONTROL_REG
|
||||
*/
|
||||
#define VI_CTRL_TYPE_16 0x00002 /* Bit [1:0] pixel size: 16 bit */
|
||||
#define VI_CTRL_TYPE_32 0x00003 /* Bit [1:0] pixel size: 32 bit */
|
||||
#define VI_CTRL_GAMMA_DITHER_ON 0x00004 /* Bit 2: default = on */
|
||||
#define VI_CTRL_GAMMA_ON 0x00008 /* Bit 3: default = on */
|
||||
#define VI_CTRL_DIVOT_ON 0x00010 /* Bit 4: default = on */
|
||||
#define VI_CTRL_SERRATE_ON 0x00040 /* Bit 6: on if interlaced */
|
||||
#define VI_CTRL_ANTIALIAS_MASK 0x00300 /* Bit [9:8] anti-alias mode */
|
||||
#define VI_CTRL_DITHER_FILTER_ON 0x10000 /* Bit 16: dither-filter mode */
|
||||
|
||||
/*
|
||||
* Possible video clocks (NTSC or PAL)
|
||||
*/
|
||||
#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
|
||||
#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
|
||||
#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Audio Interface (AI) Registers
|
||||
*
|
||||
* The address and length registers are double buffered; that is, they
|
||||
* can be written twice before becoming full.
|
||||
* The address must be written before the length.
|
||||
*/
|
||||
#define AI_BASE_REG 0x04500000
|
||||
|
||||
/* AI DRAM address (W): [23:0] starting RDRAM address (8B-aligned) */
|
||||
#define AI_DRAM_ADDR_REG (AI_BASE_REG+0x00) /* R0: DRAM address */
|
||||
|
||||
/* AI length (R/W): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored */
|
||||
/* [17:0] transfer length (v2.0) - Bottom 3 bits are ignored */
|
||||
#define AI_LEN_REG (AI_BASE_REG+0x04) /* R1: Length */
|
||||
|
||||
/* AI control (W): [0] DMA enable - if LSB == 1, DMA is enabled */
|
||||
#define AI_CONTROL_REG (AI_BASE_REG+0x08) /* R2: DMA Control */
|
||||
|
||||
/*
|
||||
* AI status (R): [31]/[0] ai_full (addr & len buffer full), [30] ai_busy
|
||||
* Note that a 1->0 transition in ai_full will set interrupt
|
||||
* (W): clear audio interrupt
|
||||
*/
|
||||
#define AI_STATUS_REG (AI_BASE_REG+0x0C) /* R3: Status */
|
||||
|
||||
/*
|
||||
* AI DAC sample period register (W): [13:0] dac rate
|
||||
* - vid_clock/(dperiod + 1) is the DAC sample rate
|
||||
* - (dperiod + 1) >= 66 * (aclockhp + 1) must be true
|
||||
*/
|
||||
#define AI_DACRATE_REG (AI_BASE_REG+0x10) /* R4: DAC rate 14-lsb*/
|
||||
|
||||
/*
|
||||
* AI bit rate (W): [3:0] bit rate (abus clock half period register - aclockhp)
|
||||
* - vid_clock/(2 * (aclockhp + 1)) is the DAC clock rate
|
||||
* - The abus clock stops if aclockhp is zero
|
||||
*/
|
||||
#define AI_BITRATE_REG (AI_BASE_REG+0x14) /* R5: Bit rate 4-lsb */
|
||||
|
||||
/* Value for control register */
|
||||
#define AI_CONTROL_DMA_ON 0x01 /* LSB = 1: DMA enable*/
|
||||
#define AI_CONTROL_DMA_OFF 0x00 /* LSB = 1: DMA enable*/
|
||||
|
||||
/* Value for status register */
|
||||
#define AI_STATUS_FIFO_FULL 0x80000000 /* Bit 31: full */
|
||||
#define AI_STATUS_DMA_BUSY 0x40000000 /* Bit 30: busy */
|
||||
|
||||
/* DAC rate = video clock / audio frequency
|
||||
* - DAC rate >= (66 * Bit rate) must be true
|
||||
*/
|
||||
#define AI_MAX_DAC_RATE 16384 /* 14-bit+1 */
|
||||
#define AI_MIN_DAC_RATE 132
|
||||
|
||||
/* Bit rate <= (DAC rate / 66) */
|
||||
#define AI_MAX_BIT_RATE 16 /* 4-bit+1 */
|
||||
#define AI_MIN_BIT_RATE 2
|
||||
|
||||
/*
|
||||
* Maximum and minimum values for audio frequency based on video clocks
|
||||
* max frequency = (video clock / min dac rate)
|
||||
* min frequency = (video clock / max dac rate)
|
||||
*/
|
||||
#define AI_NTSC_MAX_FREQ 368000 /* 368 KHz */
|
||||
#define AI_NTSC_MIN_FREQ 3000 /* 3 KHz ~ 2971 Hz */
|
||||
|
||||
#define AI_PAL_MAX_FREQ 376000 /* 376 KHz */
|
||||
#define AI_PAL_MIN_FREQ 3050 /* 3 KHz ~ 3031 Hz */
|
||||
|
||||
#define AI_MPAL_MAX_FREQ 368000 /* 368 KHz */
|
||||
#define AI_MPAL_MIN_FREQ 3000 /* 3 KHz ~ 2968 Hz */
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Peripheral Interface (PI) Registers
|
||||
*/
|
||||
#define PI_BASE_REG 0x04600000
|
||||
|
||||
/* PI DRAM address (R/W): [23:0] starting RDRAM address */
|
||||
#define PI_DRAM_ADDR_REG (PI_BASE_REG+0x00) /* DRAM address */
|
||||
|
||||
/* PI pbus (cartridge) address (R/W): [31:0] starting AD16 address */
|
||||
#define PI_CART_ADDR_REG (PI_BASE_REG+0x04)
|
||||
|
||||
/* PI read length (R/W): [23:0] read data length */
|
||||
#define PI_RD_LEN_REG (PI_BASE_REG+0x08)
|
||||
|
||||
/* PI write length (R/W): [23:0] write data length */
|
||||
#define PI_WR_LEN_REG (PI_BASE_REG+0x0C)
|
||||
|
||||
/*
|
||||
* PI status (R): [0] DMA busy, [1] IO busy, [2], error
|
||||
* (W): [0] reset controller (and abort current op), [1] clear intr
|
||||
*/
|
||||
#define PI_STATUS_REG (PI_BASE_REG+0x10)
|
||||
|
||||
/* PI dom1 latency (R/W): [7:0] domain 1 device latency */
|
||||
#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14)
|
||||
|
||||
/* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */
|
||||
#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18)
|
||||
|
||||
/* PI dom1 page size (R/W): [3:0] domain 1 device page size */
|
||||
#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */
|
||||
|
||||
/* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */
|
||||
#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20)
|
||||
|
||||
/* PI dom2 latency (R/W): [7:0] domain 2 device latency */
|
||||
#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */
|
||||
|
||||
/* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */
|
||||
#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */
|
||||
|
||||
/* PI dom2 page size (R/W): [3:0] domain 2 device page size */
|
||||
#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */
|
||||
|
||||
/* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */
|
||||
#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */
|
||||
|
||||
#define PI_DOMAIN1_REG PI_BSD_DOM1_LAT_REG
|
||||
#define PI_DOMAIN2_REG PI_BSD_DOM2_LAT_REG
|
||||
|
||||
#define PI_DOM_LAT_OFS 0x00
|
||||
#define PI_DOM_PWD_OFS 0x04
|
||||
#define PI_DOM_PGS_OFS 0x08
|
||||
#define PI_DOM_RLS_OFS 0x0C
|
||||
|
||||
/*
|
||||
* PI status register has 3 bits active when read from (PI_STATUS_REG - read)
|
||||
* Bit 0: DMA busy - set when DMA is in progress
|
||||
* Bit 1: IO busy - set when IO is in progress
|
||||
* Bit 2: Error - set when CPU issues IO request while DMA is busy
|
||||
*/
|
||||
#define PI_STATUS_ERROR 0x04
|
||||
#define PI_STATUS_IO_BUSY 0x02
|
||||
#define PI_STATUS_DMA_BUSY 0x01
|
||||
|
||||
/* PI status register has 2 bits active when written to:
|
||||
* Bit 0: When set, reset PIC
|
||||
* Bit 1: When set, clear interrupt flag
|
||||
* The values of the two bits can be ORed together to both reset PIC and
|
||||
* clear interrupt at the same time.
|
||||
*
|
||||
* Note:
|
||||
* - The PIC does generate an interrupt at the end of each DMA. CPU
|
||||
* needs to clear the interrupt flag explicitly (from an interrupt
|
||||
* handler) by writing into the STATUS register with bit 1 set.
|
||||
*
|
||||
* - When a DMA completes, the interrupt flag is set. CPU can issue
|
||||
* another request even while the interrupt flag is set (as long as
|
||||
* PIC is idle). However, it is the CPU's responsibility for
|
||||
* maintaining accurate correspondence between DMA completions and
|
||||
* interrupts.
|
||||
*
|
||||
* - When PIC is reset, if PIC happens to be busy, an interrupt will
|
||||
* be generated as PIC returns to idle. Otherwise, no interrupt will
|
||||
* be generated and PIC remains idle.
|
||||
*/
|
||||
/*
|
||||
* Values to clear interrupt/reset PIC (PI_STATUS_REG - write)
|
||||
*/
|
||||
#define PI_STATUS_RESET 0x01
|
||||
#define PI_SET_RESET PI_STATUS_RESET
|
||||
|
||||
#define PI_STATUS_CLR_INTR 0x02
|
||||
#define PI_CLR_INTR PI_STATUS_CLR_INTR
|
||||
|
||||
#define PI_DMA_BUFFER_SIZE 128
|
||||
|
||||
#define PI_DOM1_ADDR1 0x06000000 /* to 0x07FFFFFF */
|
||||
#define PI_DOM1_ADDR2 0x10000000 /* to 0x1FBFFFFF */
|
||||
#define PI_DOM1_ADDR3 0x1FD00000 /* to 0x7FFFFFFF */
|
||||
#define PI_DOM2_ADDR1 0x05000000 /* to 0x05FFFFFF */
|
||||
#define PI_DOM2_ADDR2 0x08000000 /* to 0x0FFFFFFF */
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* RDRAM Interface (RI) Registers
|
||||
*/
|
||||
#define RI_BASE_REG 0x04700000
|
||||
|
||||
/* RI mode (R/W): [1:0] operating mode, [2] stop T active, [3] stop R active */
|
||||
#define RI_MODE_REG (RI_BASE_REG+0x00)
|
||||
|
||||
/* RI config (R/W): [5:0] current control input, [6] current control enable */
|
||||
#define RI_CONFIG_REG (RI_BASE_REG+0x04)
|
||||
|
||||
/* RI current load (W): [] any write updates current control register */
|
||||
#define RI_CURRENT_LOAD_REG (RI_BASE_REG+0x08)
|
||||
|
||||
/* RI select (R/W): [2:0] receive select, [2:0] transmit select */
|
||||
#define RI_SELECT_REG (RI_BASE_REG+0x0C)
|
||||
|
||||
/* RI refresh (R/W): [7:0] clean refresh delay, [15:8] dirty refresh delay,
|
||||
* [16] refresh bank, [17] refresh enable
|
||||
* [18] refresh optimize
|
||||
*/
|
||||
#define RI_REFRESH_REG (RI_BASE_REG+0x10)
|
||||
#define RI_COUNT_REG RI_REFRESH_REG
|
||||
|
||||
/* RI latency (R/W): [3:0] DMA latency/overlap */
|
||||
#define RI_LATENCY_REG (RI_BASE_REG+0x14)
|
||||
|
||||
/* RI error (R): [0] nack error, [1] ack error */
|
||||
#define RI_RERROR_REG (RI_BASE_REG+0x18)
|
||||
|
||||
/* RI error (W): [] any write clears all error bits */
|
||||
#define RI_WERROR_REG (RI_BASE_REG+0x1C)
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Serial Interface (SI) Registers
|
||||
*/
|
||||
#define SI_BASE_REG 0x04800000
|
||||
|
||||
/* SI DRAM address (R/W): [23:0] starting RDRAM address */
|
||||
#define SI_DRAM_ADDR_REG (SI_BASE_REG+0x00) /* R0: DRAM address */
|
||||
|
||||
/* SI address read 64B (W): [] any write causes a 64B DMA write */
|
||||
#define SI_PIF_ADDR_RD64B_REG (SI_BASE_REG+0x04) /* R1: 64B PIF->DRAM */
|
||||
|
||||
/* Address SI_BASE_REG + (0x08, 0x0c, 0x14) are reserved */
|
||||
|
||||
/* SI address write 64B (W): [] any write causes a 64B DMA read */
|
||||
#define SI_PIF_ADDR_WR64B_REG (SI_BASE_REG+0x10) /* R4: 64B DRAM->PIF */
|
||||
|
||||
/*
|
||||
* SI status (W): [] any write clears interrupt
|
||||
* (R): [0] DMA busy, [1] IO read busy, [2] reserved
|
||||
* [3] DMA error, [12] interrupt
|
||||
*/
|
||||
#define SI_STATUS_REG (SI_BASE_REG+0x18) /* R6: Status */
|
||||
|
||||
/* SI status register has the following bits active:
|
||||
* 0: DMA busy - set when DMA is in progress
|
||||
* 1: IO busy - set when IO access is in progress
|
||||
* 3: DMA error - set when there are overlapping DMA requests
|
||||
* 12: Interrupt - Interrupt set
|
||||
*/
|
||||
#define SI_STATUS_DMA_BUSY 0x0001
|
||||
#define SI_STATUS_RD_BUSY 0x0002
|
||||
#define SI_STATUS_DMA_ERROR 0x0008
|
||||
#define SI_STATUS_INTERRUPT 0x1000
|
||||
|
||||
/*************************************************************************
|
||||
* Development Board GIO Control Registers
|
||||
*/
|
||||
|
||||
#define GIO_BASE_REG 0x18000000
|
||||
|
||||
/* Game to Host Interrupt */
|
||||
#define GIO_GIO_INTR_REG (GIO_BASE_REG+0x000)
|
||||
|
||||
/* Game to Host SYNC */
|
||||
#define GIO_GIO_SYNC_REG (GIO_BASE_REG+0x400)
|
||||
|
||||
/* Host to Game Interrupt */
|
||||
#define GIO_CART_INTR_REG (GIO_BASE_REG+0x800)
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Common macros
|
||||
*/
|
||||
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
|
||||
#define IO_READ(addr) (*(vu32 *)PHYS_TO_K1(addr))
|
||||
#define IO_WRITE(addr,data) (*(vu32 *)PHYS_TO_K1(addr)=(u32)(data))
|
||||
#define RCP_STAT_PRINT \
|
||||
rmonPrintf("current=%x start=%x end=%x dpstat=%x spstat=%x\n", \
|
||||
IO_READ(DPC_CURRENT_REG), \
|
||||
IO_READ(DPC_START_REG), \
|
||||
IO_READ(DPC_END_REG), \
|
||||
IO_READ(DPC_STATUS_REG), \
|
||||
IO_READ(SP_STATUS_REG))
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _RCP_H_ */
|
||||
|
||||
|
|
@ -8,7 +8,7 @@
|
|||
#define M_HVQTASK 6
|
||||
#define M_HVQMTASK 7
|
||||
|
||||
#if (defined(F3DEX_GBI) || defined(F3DLP_GBI) || defined(F3DEX_GBI_2))
|
||||
#if (defined(F3DEX_GBI) || defined(F3DLP_GBI) || defined(F3DEX_GBI_2) || 1)
|
||||
#define OS_YIELD_DATA_SIZE 0xc00
|
||||
#else
|
||||
#define OS_YIELD_DATA_SIZE 0x900
|
||||
|
|
@ -19,6 +19,15 @@
|
|||
#define M_TASK_FLAG0 1
|
||||
#define M_TASK_FLAG1 2
|
||||
|
||||
#define OS_TASK_YIELDED 0x0001
|
||||
#define OS_TASK_DP_WAIT 0x0002
|
||||
#define OS_TASK_LOADABLE 0x0004
|
||||
#define OS_TASK_SP_ONLY 0x0008
|
||||
#define OS_TASK_USR0 0x0010
|
||||
#define OS_TASK_USR1 0x0020
|
||||
#define OS_TASK_USR2 0x0040
|
||||
#define OS_TASK_USR3 0x0080
|
||||
|
||||
/* SpStatus */
|
||||
#define SPSTATUS_CLEAR_HALT 0x00000001
|
||||
#define SPSTATUS_SET_HALT 0x00000002
|
||||
|
|
|
|||
|
|
@ -3,6 +3,4 @@
|
|||
#include <ultra64.h>
|
||||
#include "types.h"
|
||||
|
||||
u32 func00005e40(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -3,7 +3,4 @@
|
|||
#include <ultra64.h>
|
||||
#include "types.h"
|
||||
|
||||
u32 func0004b500(void);
|
||||
u32 func0004b510(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -3,6 +3,4 @@
|
|||
#include <ultra64.h>
|
||||
#include "types.h"
|
||||
|
||||
u32 func0004b550(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -3,6 +3,4 @@
|
|||
#include <ultra64.h>
|
||||
#include "types.h"
|
||||
|
||||
u32 func0004b5e0(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -34,10 +34,10 @@ s32 __osSiRawWriteIo(void*, u32);
|
|||
s32 osPiRawReadIo(u32 a0, u32 *a1);
|
||||
void __osSpSetStatus(u32);
|
||||
u32 __osSpGetStatus();
|
||||
s32 __osSpSetPc(void*);
|
||||
s32 __osSpSetPc(u32);
|
||||
s32 __osSpDeviceBusy();
|
||||
s32 __osSiDeviceBusy();
|
||||
s32 __osSpRawStartDma(u32 dir, void *sp_ptr, void *dram_ptr, size_t size);
|
||||
s32 __osSpRawStartDma(u32 dir, u32 sp_ptr, void *dram_ptr, size_t size);
|
||||
void __osViInit();
|
||||
OSViContext * __osViGetCurrentContext();
|
||||
void __osViSwapContext();
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include <PR/os_ai.h>
|
||||
#include <PR/libaudio.h>
|
||||
#include <PR/libultra.h>
|
||||
#include <PR/rcp.h>
|
||||
#include <PR/sched.h>
|
||||
|
||||
#define OS_K0_TO_PHYSICAL(x) (u32)(((char *)(x)-0x80000000))
|
||||
|
|
|
|||
|
|
@ -14,9 +14,12 @@
|
|||
#include "lib/lib_4b550.h"
|
||||
#include "lib/lib_4b5e0.h"
|
||||
#include "types.h"
|
||||
#include "libultra_internal.h"
|
||||
|
||||
OSTask *_VirtualToPhysicalTask(OSTask *intp);
|
||||
|
||||
GLOBAL_ASM(
|
||||
glabel func00005e40
|
||||
glabel _VirtualToPhysicalTask
|
||||
/* 5e40: 27bdffe8 */ addiu $sp,$sp,-24
|
||||
/* 5e44: afbf0014 */ sw $ra,0x14($sp)
|
||||
/* 5e48: 3c058009 */ lui $a1,%hi(var80090a70)
|
||||
|
|
@ -93,124 +96,48 @@ glabel func00005e40
|
|||
/* 5f48: 27bd0018 */ addiu $sp,$sp,0x18
|
||||
);
|
||||
|
||||
GLOBAL_ASM(
|
||||
glabel osSpTaskLoad
|
||||
/* 5f4c: 27bdffd8 */ addiu $sp,$sp,-40
|
||||
/* 5f50: afbf0024 */ sw $ra,0x24($sp)
|
||||
/* 5f54: afb00014 */ sw $s0,0x14($sp)
|
||||
/* 5f58: 00808025 */ or $s0,$a0,$zero
|
||||
/* 5f5c: afb30020 */ sw $s3,0x20($sp)
|
||||
/* 5f60: afb2001c */ sw $s2,0x1c($sp)
|
||||
/* 5f64: 0c001790 */ jal func00005e40
|
||||
/* 5f68: afb10018 */ sw $s1,0x18($sp)
|
||||
/* 5f6c: 8c4e0004 */ lw $t6,0x4($v0)
|
||||
/* 5f70: 00409025 */ or $s2,$v0,$zero
|
||||
/* 5f74: 02402025 */ or $a0,$s2,$zero
|
||||
/* 5f78: 31cf0001 */ andi $t7,$t6,0x1
|
||||
/* 5f7c: 11e00013 */ beqz $t7,.L00005fcc
|
||||
/* 5f80: 00000000 */ nop
|
||||
/* 5f84: 8c580038 */ lw $t8,0x38($v0)
|
||||
/* 5f88: 8c59003c */ lw $t9,0x3c($v0)
|
||||
/* 5f8c: 2401fffe */ addiu $at,$zero,-2
|
||||
/* 5f90: ac580018 */ sw $t8,0x18($v0)
|
||||
/* 5f94: ac59001c */ sw $t9,0x1c($v0)
|
||||
/* 5f98: 8e080004 */ lw $t0,0x4($s0)
|
||||
/* 5f9c: 01014824 */ and $t1,$t0,$at
|
||||
/* 5fa0: ae090004 */ sw $t1,0x4($s0)
|
||||
/* 5fa4: 8c4a0004 */ lw $t2,0x4($v0)
|
||||
/* 5fa8: 314b0004 */ andi $t3,$t2,0x4
|
||||
/* 5fac: 11600007 */ beqz $t3,.L00005fcc
|
||||
/* 5fb0: 00000000 */ nop
|
||||
/* 5fb4: 8e0c0038 */ lw $t4,0x38($s0)
|
||||
/* 5fb8: 3c01a000 */ lui $at,0xa000
|
||||
/* 5fbc: 258d0bfc */ addiu $t5,$t4,0xbfc
|
||||
/* 5fc0: 01a17025 */ or $t6,$t5,$at
|
||||
/* 5fc4: 8dcf0000 */ lw $t7,0x0($t6)
|
||||
/* 5fc8: ac4f0010 */ sw $t7,0x10($v0)
|
||||
.L00005fcc:
|
||||
/* 5fcc: 0c012b60 */ jal osWritebackDCache
|
||||
/* 5fd0: 24050040 */ addiu $a1,$zero,0x40
|
||||
/* 5fd4: 0c012d40 */ jal func0004b500
|
||||
/* 5fd8: 24042b00 */ addiu $a0,$zero,0x2b00
|
||||
/* 5fdc: 3c130400 */ lui $s3,0x400
|
||||
/* 5fe0: 36731000 */ ori $s3,$s3,0x1000
|
||||
/* 5fe4: 0c012d44 */ jal func0004b510
|
||||
/* 5fe8: 02602025 */ or $a0,$s3,$zero
|
||||
/* 5fec: 2411ffff */ addiu $s1,$zero,-1
|
||||
/* 5ff0: 54510006 */ bnel $v0,$s1,.L0000600c
|
||||
/* 5ff4: 3c100400 */ lui $s0,0x400
|
||||
.L00005ff8:
|
||||
/* 5ff8: 0c012d44 */ jal func0004b510
|
||||
/* 5ffc: 02602025 */ or $a0,$s3,$zero
|
||||
/* 6000: 1051fffd */ beq $v0,$s1,.L00005ff8
|
||||
/* 6004: 00000000 */ nop
|
||||
/* 6008: 3c100400 */ lui $s0,0x400
|
||||
.L0000600c:
|
||||
/* 600c: 36100fc0 */ ori $s0,$s0,0xfc0
|
||||
/* 6010: 02002825 */ or $a1,$s0,$zero
|
||||
/* 6014: 24040001 */ addiu $a0,$zero,0x1
|
||||
/* 6018: 02403025 */ or $a2,$s2,$zero
|
||||
/* 601c: 0c012d54 */ jal func0004b550
|
||||
/* 6020: 24070040 */ addiu $a3,$zero,0x40
|
||||
/* 6024: 14510007 */ bne $v0,$s1,.L00006044
|
||||
/* 6028: 24040001 */ addiu $a0,$zero,0x1
|
||||
.L0000602c:
|
||||
/* 602c: 02002825 */ or $a1,$s0,$zero
|
||||
/* 6030: 02403025 */ or $a2,$s2,$zero
|
||||
/* 6034: 0c012d54 */ jal func0004b550
|
||||
/* 6038: 24070040 */ addiu $a3,$zero,0x40
|
||||
/* 603c: 5051fffb */ beql $v0,$s1,.L0000602c
|
||||
/* 6040: 24040001 */ addiu $a0,$zero,0x1
|
||||
.L00006044:
|
||||
/* 6044: 0c012d78 */ jal func0004b5e0
|
||||
/* 6048: 00000000 */ nop
|
||||
/* 604c: 50400006 */ beqzl $v0,.L00006068
|
||||
/* 6050: 24040001 */ addiu $a0,$zero,0x1
|
||||
.L00006054:
|
||||
/* 6054: 0c012d78 */ jal func0004b5e0
|
||||
/* 6058: 00000000 */ nop
|
||||
/* 605c: 1440fffd */ bnez $v0,.L00006054
|
||||
/* 6060: 00000000 */ nop
|
||||
/* 6064: 24040001 */ addiu $a0,$zero,0x1
|
||||
.L00006068:
|
||||
/* 6068: 02602825 */ or $a1,$s3,$zero
|
||||
/* 606c: 8e460008 */ lw $a2,0x8($s2)
|
||||
/* 6070: 0c012d54 */ jal func0004b550
|
||||
/* 6074: 8e47000c */ lw $a3,0xc($s2)
|
||||
/* 6078: 14510007 */ bne $v0,$s1,.L00006098
|
||||
/* 607c: 24040001 */ addiu $a0,$zero,0x1
|
||||
.L00006080:
|
||||
/* 6080: 02602825 */ or $a1,$s3,$zero
|
||||
/* 6084: 8e460008 */ lw $a2,0x8($s2)
|
||||
/* 6088: 0c012d54 */ jal func0004b550
|
||||
/* 608c: 8e47000c */ lw $a3,0xc($s2)
|
||||
/* 6090: 5051fffb */ beql $v0,$s1,.L00006080
|
||||
/* 6094: 24040001 */ addiu $a0,$zero,0x1
|
||||
.L00006098:
|
||||
/* 6098: 8fbf0024 */ lw $ra,0x24($sp)
|
||||
/* 609c: 8fb00014 */ lw $s0,0x14($sp)
|
||||
/* 60a0: 8fb10018 */ lw $s1,0x18($sp)
|
||||
/* 60a4: 8fb2001c */ lw $s2,0x1c($sp)
|
||||
/* 60a8: 8fb30020 */ lw $s3,0x20($sp)
|
||||
/* 60ac: 03e00008 */ jr $ra
|
||||
/* 60b0: 27bd0028 */ addiu $sp,$sp,0x28
|
||||
);
|
||||
void osSpTaskLoad(OSTask *intp)
|
||||
{
|
||||
OSTask *tp;
|
||||
tp = _VirtualToPhysicalTask(intp);
|
||||
|
||||
if (tp->t.flags & OS_TASK_YIELDED) {
|
||||
tp->t.ucode_data = tp->t.yield_data_ptr;
|
||||
tp->t.ucode_data_size = tp->t.yield_data_size;
|
||||
intp->t.flags &= ~OS_TASK_YIELDED;
|
||||
|
||||
if (tp->t.flags & OS_TASK_LOADABLE) {
|
||||
tp->t.ucode = (u64 *)IO_READ((u32)intp->t.yield_data_ptr + OS_YIELD_DATA_SIZE - 4);
|
||||
}
|
||||
}
|
||||
|
||||
osWritebackDCache(tp, sizeof(OSTask));
|
||||
__osSpSetStatus(SP_CLR_YIELD | SP_CLR_YIELDED | SP_CLR_TASKDONE | SP_SET_INTR_BREAK);
|
||||
|
||||
while (__osSpSetPc(SP_IMEM_START) == -1);
|
||||
|
||||
while (__osSpRawStartDma(1, (SP_IMEM_START - sizeof(*tp)), tp, sizeof(OSTask)) == -1);
|
||||
|
||||
while (__osSpDeviceBusy());
|
||||
|
||||
while (__osSpRawStartDma(1, SP_IMEM_START, tp->t.ucode_boot, tp->t.ucode_boot_size) == -1);
|
||||
}
|
||||
|
||||
GLOBAL_ASM(
|
||||
glabel osSpTaskStartGo
|
||||
/* 60b4: 27bdffe8 */ addiu $sp,$sp,-24
|
||||
/* 60b8: afbf0014 */ sw $ra,0x14($sp)
|
||||
/* 60bc: 0c012d78 */ jal func0004b5e0
|
||||
/* 60bc: 0c012d78 */ jal __osSpDeviceBusy
|
||||
/* 60c0: afa40018 */ sw $a0,0x18($sp)
|
||||
/* 60c4: 10400005 */ beqz $v0,.L000060dc
|
||||
/* 60c8: 00000000 */ nop
|
||||
.L000060cc:
|
||||
/* 60cc: 0c012d78 */ jal func0004b5e0
|
||||
/* 60cc: 0c012d78 */ jal __osSpDeviceBusy
|
||||
/* 60d0: 00000000 */ nop
|
||||
/* 60d4: 1440fffd */ bnez $v0,.L000060cc
|
||||
/* 60d8: 00000000 */ nop
|
||||
.L000060dc:
|
||||
/* 60dc: 0c012d40 */ jal func0004b500
|
||||
/* 60dc: 0c012d40 */ jal __osSpSetStatus
|
||||
/* 60e0: 24040125 */ addiu $a0,$zero,0x125
|
||||
/* 60e4: 8fbf0014 */ lw $ra,0x14($sp)
|
||||
/* 60e8: 27bd0018 */ addiu $sp,$sp,0x18
|
||||
|
|
@ -219,4 +146,4 @@ glabel osSpTaskStartGo
|
|||
/* 60f4: 00000000 */ nop
|
||||
/* 60f8: 00000000 */ nop
|
||||
/* 60fc: 00000000 */ nop
|
||||
);
|
||||
);
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ GLOBAL_ASM(
|
|||
glabel func00049100
|
||||
/* 49100: 27bdffe8 */ addiu $sp,$sp,-24
|
||||
/* 49104: afbf0014 */ sw $ra,0x14($sp)
|
||||
/* 49108: 0c012d40 */ jal func0004b500
|
||||
/* 49108: 0c012d40 */ jal __osSpSetStatus
|
||||
/* 4910c: 24040400 */ addiu $a0,$zero,0x400
|
||||
/* 49110: 8fbf0014 */ lw $ra,0x14($sp)
|
||||
/* 49114: 27bd0018 */ addiu $sp,$sp,0x18
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
#include "types.h"
|
||||
|
||||
GLOBAL_ASM(
|
||||
glabel func0004b500
|
||||
glabel __osSpSetStatus
|
||||
/* 4b500: 3c0ea404 */ lui $t6,0xa404
|
||||
/* 4b504: 03e00008 */ jr $ra
|
||||
/* 4b508: adc40010 */ sw $a0,0x10($t6)
|
||||
|
|
@ -19,7 +19,7 @@ glabel func0004b500
|
|||
);
|
||||
|
||||
GLOBAL_ASM(
|
||||
glabel func0004b510
|
||||
glabel __osSpSetPc
|
||||
/* 4b510: 3c0ea404 */ lui $t6,0xa404
|
||||
/* 4b514: 8dc50010 */ lw $a1,0x10($t6)
|
||||
/* 4b518: 27bdfff8 */ addiu $sp,$sp,-8
|
||||
|
|
|
|||
|
|
@ -12,13 +12,13 @@
|
|||
#include "types.h"
|
||||
|
||||
GLOBAL_ASM(
|
||||
glabel func0004b550
|
||||
glabel __osSpRawStartDma
|
||||
/* 4b550: 27bdffe8 */ addiu $sp,$sp,-24
|
||||
/* 4b554: afbf0014 */ sw $ra,0x14($sp)
|
||||
/* 4b558: afa40018 */ sw $a0,0x18($sp)
|
||||
/* 4b55c: afa5001c */ sw $a1,0x1c($sp)
|
||||
/* 4b560: afa60020 */ sw $a2,0x20($sp)
|
||||
/* 4b564: 0c012d78 */ jal func0004b5e0
|
||||
/* 4b564: 0c012d78 */ jal __osSpDeviceBusy
|
||||
/* 4b568: afa70024 */ sw $a3,0x24($sp)
|
||||
/* 4b56c: 10400003 */ beqz $v0,.L0004b57c
|
||||
/* 4b570: 8fae001c */ lw $t6,0x1c($sp)
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
#include "types.h"
|
||||
|
||||
GLOBAL_ASM(
|
||||
glabel func0004b5e0
|
||||
glabel __osSpDeviceBusy
|
||||
/* 4b5e0: 3c0ea404 */ lui $t6,0xa404
|
||||
/* 4b5e4: 8dc40010 */ lw $a0,0x10($t6)
|
||||
/* 4b5e8: 27bdfff8 */ addiu $sp,$sp,-8
|
||||
|
|
|
|||
Loading…
Reference in New Issue