diff --git a/src/include/PR/os_misc.h b/src/include/PR/os_misc.h
index 8f5c2171d..80a0ef070 100644
--- a/src/include/PR/os_misc.h
+++ b/src/include/PR/os_misc.h
@@ -97,6 +97,12 @@ typedef char *va_list;
 #define EEP16K_MAXBLOCKS	256
 #define EEPROM_BLOCK_SIZE	8
 
+/*
+ * PI/EPI
+ */
+#define PI_DOMAIN1      0
+#define PI_DOMAIN2      1
+
 /* Miscellaneous OS functions */
 
 void osInitialize(void);
diff --git a/src/include/PR/os_pi.h b/src/include/PR/os_pi.h
index 6592c5ce1..ac83a8296 100644
--- a/src/include/PR/os_pi.h
+++ b/src/include/PR/os_pi.h
@@ -88,6 +88,10 @@ typedef struct {
     while (stat & (PI_STATUS_IO_BUSY | PI_STATUS_DMA_BUSY)) \
         stat = IO_READ(PI_STATUS_REG);
 
+#define UPDATE_REG(reg, var)           \
+    if (cHandle->var != pihandle->var) \
+        IO_WRITE(reg, pihandle->var);
+
 /* Functions */
 
 s32 osPiStartDma(OSIoMesg *mb, s32 priority, s32 direction,
diff --git a/src/lib/ultra/io/epirawdma.c b/src/lib/ultra/io/epirawdma.c
index 1ac0b2d79..a77218708 100644
--- a/src/lib/ultra/io/epirawdma.c
+++ b/src/lib/ultra/io/epirawdma.c
@@ -140,3 +140,49 @@ glabel osEPiRawStartDma
 /*    49df8:	03e00008 */ 	jr	$ra
 /*    49dfc:	00000000 */ 	nop
 );
+
+// Mismatch: branch/branch-likely
+//s32 osEPiRawStartDma(OSPiHandle *pihandle, s32 direction, u32 devAddr, void *dramAddr, u32 size)
+//{
+//	u32 stat;
+//
+//    WAIT_ON_IOBUSY(stat)
+//
+//	if (pihandle->type != __osCurrentHandle[pihandle->domain]->type) {
+//		OSPiHandle *cHandle = __osCurrentHandle[pihandle->domain];
+//
+//		if (pihandle->domain == PI_DOMAIN1) {
+//			UPDATE_REG(PI_BSD_DOM1_LAT_REG, latency);
+//			UPDATE_REG(PI_BSD_DOM1_PGS_REG, pageSize);
+//			UPDATE_REG(PI_BSD_DOM1_RLS_REG, relDuration);
+//			UPDATE_REG(PI_BSD_DOM1_PWD_REG, pulse);
+//		} else {
+//			UPDATE_REG(PI_BSD_DOM2_LAT_REG, latency);
+//			UPDATE_REG(PI_BSD_DOM2_PGS_REG, pageSize);
+//			UPDATE_REG(PI_BSD_DOM2_RLS_REG, relDuration);
+//			UPDATE_REG(PI_BSD_DOM2_PWD_REG, pulse);
+//		}
+//
+//		cHandle->type = pihandle->type;
+//		cHandle->latency = pihandle->latency;
+//		cHandle->pageSize = pihandle->pageSize;
+//		cHandle->relDuration = pihandle->relDuration;
+//		cHandle->pulse = pihandle->pulse;
+//	}
+//
+//	IO_WRITE(PI_DRAM_ADDR_REG, osVirtualToPhysical(dramAddr));
+//	IO_WRITE(PI_CART_ADDR_REG, K1_TO_PHYS(pihandle->baseAddress | devAddr));
+//
+//	switch (direction) {
+//	case OS_READ:
+//		IO_WRITE(PI_WR_LEN_REG, size - 1);
+//		break;
+//	case OS_WRITE:
+//		IO_WRITE(PI_RD_LEN_REG, size - 1);
+//		break;
+//	default:
+//		return -1;
+//	}
+//
+//	return 0;
+//}