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Sparc arm/mips/sparc register patch, by Martin Bochnig. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2377 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-02-02 01:03:34 +00:00
parent 6a1cbf68b7
commit 01d6a890b4
3 changed files with 39 additions and 0 deletions
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7
target-arm/exec.h
View File

@ -19,10 +19,17 @@
*/
#include "dyngen-exec.h"
#if defined(__sparc__)
struct CPUARMState *env;
uint32_t T0;
uint32_t T1;
uint32_t T2;
#else
register struct CPUARMState *env asm(AREG0);
register uint32_t T0 asm(AREG1);
register uint32_t T1 asm(AREG2);
register uint32_t T2 asm(AREG3);
#endif
/* TODO: Put these in FP regs on targets that have such things. */
/* It is ok for FT0s and FT0d to overlap. Likewise FT1s and FT1d. */

10
target-mips/exec.h
View File

@ -7,7 +7,11 @@
#include "mips-defs.h"
#include "dyngen-exec.h"
#if defined(__sparc__)
struct CPUMIPSState *env;
#else
register struct CPUMIPSState *env asm(AREG0);
#endif
#if defined (USE_64BITS_REGS)
typedef int64_t host_int_t;
@ -17,6 +21,11 @@ typedef int32_t host_int_t;
typedef uint32_t host_uint_t;
#endif
#if defined(__sparc__)
host_uint_t T0;
host_uint_t T1;
host_uint_t T2;
#else
#if TARGET_LONG_BITS > HOST_LONG_BITS
#define T0 (env->t0)
#define T1 (env->t1)
@ -26,6 +35,7 @@ register host_uint_t T0 asm(AREG1);
register host_uint_t T1 asm(AREG2);
register host_uint_t T2 asm(AREG3);
#endif
#endif
#if defined (USE_HOST_FLOAT_REGS)
#error "implement me."

22
target-sparc/exec.h
View File

@ -3,23 +3,41 @@
#include "dyngen-exec.h"
#include "config.h"
#if defined(__sparc__)
struct CPUSPARCState *env;
#else
register struct CPUSPARCState *env asm(AREG0);
#endif
#ifdef TARGET_SPARC64
#define T0 (env->t0)
#define T1 (env->t1)
#define T2 (env->t2)
#define REGWPTR env->regwptr
#else
#if defined(__sparc__)
register uint32_t T0 asm(AREG3);
register uint32_t T1 asm(AREG2);
#else
register uint32_t T0 asm(AREG1);
register uint32_t T1 asm(AREG2);
#endif
#undef REG_REGWPTR // Broken
#ifdef REG_REGWPTR
#if defined(__sparc__)
register uint32_t *REGWPTR asm(AREG4);
#else
register uint32_t *REGWPTR asm(AREG3);
#endif
#define reg_REGWPTR
#ifdef AREG4
#if defined(__sparc__)
register uint32_t T2 asm(AREG0);
#else
register uint32_t T2 asm(AREG4);
#endif
#define reg_T2
#else
#define T2 (env->t2)
@ -27,7 +45,11 @@ register uint32_t T2 asm(AREG4);
#else
#define REGWPTR env->regwptr
#if defined(__sparc__)
register uint32_t T2 asm(AREG0);
#else
register uint32_t T2 asm(AREG3);
#endif
#define reg_T2
#endif
#endif