converted MUL/IMUL to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4508 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
30898801ad
commit
0211e5aff9
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@ -1609,22 +1609,6 @@ void helper_rsm(void)
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#endif /* !CONFIG_USER_ONLY */
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#ifdef BUGGY_GCC_DIV64
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/* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
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call it from another function */
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uint32_t div32(uint64_t *q_ptr, uint64_t num, uint32_t den)
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{
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*q_ptr = num / den;
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return num % den;
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}
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int32_t idiv32(int64_t *q_ptr, int64_t num, int32_t den)
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{
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*q_ptr = num / den;
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return num % den;
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}
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#endif
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/* division, flags are undefined */
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void helper_divb_AL(target_ulong t0)
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@ -1707,12 +1691,8 @@ void helper_divl_EAX(target_ulong t0)
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if (den == 0) {
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raise_exception(EXCP00_DIVZ);
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}
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#ifdef BUGGY_GCC_DIV64
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r = div32(&q, num, den);
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#else
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q = (num / den);
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r = (num % den);
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#endif
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if (q > 0xffffffff)
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raise_exception(EXCP00_DIVZ);
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EAX = (uint32_t)q;
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@ -1729,12 +1709,8 @@ void helper_idivl_EAX(target_ulong t0)
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if (den == 0) {
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raise_exception(EXCP00_DIVZ);
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}
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#ifdef BUGGY_GCC_DIV64
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r = idiv32(&q, num, den);
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#else
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q = (num / den);
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r = (num % den);
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#endif
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if (q != (int32_t)q)
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raise_exception(EXCP00_DIVZ);
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EAX = (uint32_t)q;
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@ -123,104 +123,6 @@
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#endif
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/* multiply/divide */
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/* XXX: add eflags optimizations */
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/* XXX: add non P4 style flags */
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void OPPROTO op_mulb_AL_T0(void)
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{
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unsigned int res;
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res = (uint8_t)EAX * (uint8_t)T0;
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EAX = (EAX & ~0xffff) | res;
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CC_DST = res;
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CC_SRC = (res & 0xff00);
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}
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void OPPROTO op_imulb_AL_T0(void)
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{
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int res;
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res = (int8_t)EAX * (int8_t)T0;
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EAX = (EAX & ~0xffff) | (res & 0xffff);
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CC_DST = res;
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CC_SRC = (res != (int8_t)res);
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}
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void OPPROTO op_mulw_AX_T0(void)
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{
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unsigned int res;
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res = (uint16_t)EAX * (uint16_t)T0;
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EAX = (EAX & ~0xffff) | (res & 0xffff);
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EDX = (EDX & ~0xffff) | ((res >> 16) & 0xffff);
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CC_DST = res;
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CC_SRC = res >> 16;
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}
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void OPPROTO op_imulw_AX_T0(void)
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{
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int res;
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res = (int16_t)EAX * (int16_t)T0;
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EAX = (EAX & ~0xffff) | (res & 0xffff);
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EDX = (EDX & ~0xffff) | ((res >> 16) & 0xffff);
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CC_DST = res;
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CC_SRC = (res != (int16_t)res);
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}
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void OPPROTO op_mull_EAX_T0(void)
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{
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uint64_t res;
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res = (uint64_t)((uint32_t)EAX) * (uint64_t)((uint32_t)T0);
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EAX = (uint32_t)res;
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EDX = (uint32_t)(res >> 32);
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CC_DST = (uint32_t)res;
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CC_SRC = (uint32_t)(res >> 32);
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}
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void OPPROTO op_imull_EAX_T0(void)
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{
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int64_t res;
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res = (int64_t)((int32_t)EAX) * (int64_t)((int32_t)T0);
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EAX = (uint32_t)(res);
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EDX = (uint32_t)(res >> 32);
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CC_DST = res;
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CC_SRC = (res != (int32_t)res);
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}
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void OPPROTO op_imulw_T0_T1(void)
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{
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int res;
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res = (int16_t)T0 * (int16_t)T1;
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T0 = res;
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CC_DST = res;
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CC_SRC = (res != (int16_t)res);
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}
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void OPPROTO op_imull_T0_T1(void)
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{
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int64_t res;
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res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1);
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T0 = res;
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CC_DST = res;
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CC_SRC = (res != (int32_t)res);
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}
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#ifdef TARGET_X86_64
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void OPPROTO op_mulq_EAX_T0(void)
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{
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helper_mulq_EAX_T0(T0);
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}
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void OPPROTO op_imulq_EAX_T0(void)
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{
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helper_imulq_EAX_T0(T0);
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}
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void OPPROTO op_imulq_T0_T1(void)
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{
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T0 = helper_imulq_T0_T1(T0, T1);
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}
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#endif
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/* constant load & misc op */
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/* XXX: consistent names */
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@ -3799,21 +3799,64 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
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case 4: /* mul */
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switch(ot) {
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case OT_BYTE:
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gen_op_mulb_AL_T0();
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gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
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tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
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/* XXX: use 32 bit mul which could be faster */
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tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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gen_op_mov_reg_T0(OT_WORD, R_EAX);
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tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
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tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
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s->cc_op = CC_OP_MULB;
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break;
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case OT_WORD:
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gen_op_mulw_AX_T0();
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gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
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tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
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/* XXX: use 32 bit mul which could be faster */
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tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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gen_op_mov_reg_T0(OT_WORD, R_EAX);
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tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
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tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
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gen_op_mov_reg_T0(OT_WORD, R_EDX);
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tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
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s->cc_op = CC_OP_MULW;
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break;
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default:
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case OT_LONG:
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gen_op_mull_EAX_T0();
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#ifdef TARGET_X86_64
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gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
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tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
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tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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gen_op_mov_reg_T0(OT_LONG, R_EAX);
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tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
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tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
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gen_op_mov_reg_T0(OT_LONG, R_EDX);
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tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
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#else
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{
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TCGv t0, t1;
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t0 = tcg_temp_new(TCG_TYPE_I64);
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t1 = tcg_temp_new(TCG_TYPE_I64);
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gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
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tcg_gen_extu_i32_i64(t0, cpu_T[0]);
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tcg_gen_extu_i32_i64(t1, cpu_T[1]);
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tcg_gen_mul_i64(t0, t0, t1);
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tcg_gen_trunc_i64_i32(cpu_T[0], t0);
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gen_op_mov_reg_T0(OT_LONG, R_EAX);
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tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
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tcg_gen_shri_i64(t0, t0, 32);
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tcg_gen_trunc_i64_i32(cpu_T[0], t0);
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gen_op_mov_reg_T0(OT_LONG, R_EDX);
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tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
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}
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#endif
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s->cc_op = CC_OP_MULL;
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break;
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#ifdef TARGET_X86_64
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case OT_QUAD:
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gen_op_mulq_EAX_T0();
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tcg_gen_helper_0_1(helper_mulq_EAX_T0, cpu_T[0]);
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s->cc_op = CC_OP_MULQ;
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break;
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#endif
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@ -3822,21 +3865,68 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
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case 5: /* imul */
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switch(ot) {
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case OT_BYTE:
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gen_op_imulb_AL_T0();
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gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
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tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
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/* XXX: use 32 bit mul which could be faster */
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tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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gen_op_mov_reg_T0(OT_WORD, R_EAX);
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tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
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tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
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tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
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s->cc_op = CC_OP_MULB;
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break;
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case OT_WORD:
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gen_op_imulw_AX_T0();
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gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
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tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
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/* XXX: use 32 bit mul which could be faster */
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tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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gen_op_mov_reg_T0(OT_WORD, R_EAX);
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tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
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tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
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tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
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tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
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gen_op_mov_reg_T0(OT_WORD, R_EDX);
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s->cc_op = CC_OP_MULW;
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break;
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default:
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case OT_LONG:
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gen_op_imull_EAX_T0();
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#ifdef TARGET_X86_64
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gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
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tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
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tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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gen_op_mov_reg_T0(OT_LONG, R_EAX);
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tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
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tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
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tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
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tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
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gen_op_mov_reg_T0(OT_LONG, R_EDX);
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#else
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{
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TCGv t0, t1;
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t0 = tcg_temp_new(TCG_TYPE_I64);
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t1 = tcg_temp_new(TCG_TYPE_I64);
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gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
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tcg_gen_ext_i32_i64(t0, cpu_T[0]);
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tcg_gen_ext_i32_i64(t1, cpu_T[1]);
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tcg_gen_mul_i64(t0, t0, t1);
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tcg_gen_trunc_i64_i32(cpu_T[0], t0);
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gen_op_mov_reg_T0(OT_LONG, R_EAX);
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tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
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tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
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tcg_gen_shri_i64(t0, t0, 32);
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tcg_gen_trunc_i64_i32(cpu_T[0], t0);
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gen_op_mov_reg_T0(OT_LONG, R_EDX);
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tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
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}
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#endif
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s->cc_op = CC_OP_MULL;
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break;
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#ifdef TARGET_X86_64
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case OT_QUAD:
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gen_op_imulq_EAX_T0();
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tcg_gen_helper_0_1(helper_imulq_EAX_T0, cpu_T[0]);
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s->cc_op = CC_OP_MULQ;
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break;
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#endif
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@ -4104,13 +4194,41 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
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#ifdef TARGET_X86_64
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if (ot == OT_QUAD) {
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gen_op_imulq_T0_T1();
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tcg_gen_helper_1_2(helper_imulq_T0_T1, cpu_T[0], cpu_T[0], cpu_T[1]);
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} else
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#endif
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if (ot == OT_LONG) {
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gen_op_imull_T0_T1();
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#ifdef TARGET_X86_64
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tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
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tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
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tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
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tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
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#else
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{
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TCGv t0, t1;
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t0 = tcg_temp_new(TCG_TYPE_I64);
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t1 = tcg_temp_new(TCG_TYPE_I64);
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tcg_gen_ext_i32_i64(t0, cpu_T[0]);
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tcg_gen_ext_i32_i64(t1, cpu_T[1]);
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tcg_gen_mul_i64(t0, t0, t1);
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tcg_gen_trunc_i64_i32(cpu_T[0], t0);
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tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
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tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
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tcg_gen_shri_i64(t0, t0, 32);
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tcg_gen_trunc_i64_i32(cpu_T[1], t0);
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tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
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}
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#endif
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} else {
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gen_op_imulw_T0_T1();
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tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
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/* XXX: use 32 bit mul which could be faster */
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tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
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tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
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tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
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}
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gen_op_mov_reg_T0(ot, reg);
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s->cc_op = CC_OP_MULB + ot;
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