Revert "spapr_pci: map the MSI window in each PHB"
This patch is predicated on cc943c, which was dropped from
stable tree for other reasons.
This reverts commit 0824ca6bd1
.
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
This commit is contained in:
parent
3cb451edb2
commit
07178559a9
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@ -1377,6 +1377,7 @@ static void ppc_spapr_init(MachineState *machine)
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spapr_create_nvram(spapr);
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spapr_create_nvram(spapr);
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/* Set up PCI */
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/* Set up PCI */
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spapr_pci_msi_init(spapr, SPAPR_PCI_MSI_WINDOW);
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spapr_pci_rtas_init();
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spapr_pci_rtas_init();
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phb = spapr_create_phb(spapr, 0);
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phb = spapr_create_phb(spapr, 0);
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@ -341,7 +341,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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}
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}
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/* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
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/* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
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spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
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spapr_msi_setmsg(pdev, spapr->msi_win_addr, ret_intr_type == RTAS_TYPE_MSIX,
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irq, req_num);
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irq, req_num);
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/* Add MSI device to cache */
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/* Add MSI device to cache */
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@ -465,6 +465,34 @@ static const MemoryRegionOps spapr_msi_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN
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.endianness = DEVICE_LITTLE_ENDIAN
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};
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};
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void spapr_pci_msi_init(sPAPREnvironment *spapr, hwaddr addr)
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{
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uint64_t window_size = 4096;
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/*
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* As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
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* we need to allocate some memory to catch those writes coming
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* from msi_notify()/msix_notify().
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* As MSIMessage:addr is going to be the same and MSIMessage:data
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* is going to be a VIRQ number, 4 bytes of the MSI MR will only
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* be used.
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*
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* For KVM we want to ensure that this memory is a full page so that
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* our memory slot is of page size granularity.
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*/
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#ifdef CONFIG_KVM
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if (kvm_enabled()) {
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window_size = getpagesize();
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}
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#endif
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spapr->msi_win_addr = addr;
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memory_region_init_io(&spapr->msiwindow, NULL, &spapr_msi_ops, spapr,
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"msi", window_size);
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memory_region_add_subregion(get_system_memory(), spapr->msi_win_addr,
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&spapr->msiwindow);
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}
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/*
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/*
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* PHB PCI device
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* PHB PCI device
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*/
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*/
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@ -484,7 +512,6 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
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char *namebuf;
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char *namebuf;
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int i;
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int i;
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PCIBus *bus;
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PCIBus *bus;
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uint64_t msi_window_size = 4096;
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if (sphb->index != -1) {
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if (sphb->index != -1) {
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hwaddr windows_base;
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hwaddr windows_base;
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@ -577,28 +604,6 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
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address_space_init(&sphb->iommu_as, &sphb->iommu_root,
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address_space_init(&sphb->iommu_as, &sphb->iommu_root,
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sphb->dtbusname);
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sphb->dtbusname);
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/*
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* As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
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* we need to allocate some memory to catch those writes coming
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* from msi_notify()/msix_notify().
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* As MSIMessage:addr is going to be the same and MSIMessage:data
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* is going to be a VIRQ number, 4 bytes of the MSI MR will only
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* be used.
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*
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* For KVM we want to ensure that this memory is a full page so that
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* our memory slot is of page size granularity.
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*/
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#ifdef CONFIG_KVM
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if (kvm_enabled()) {
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msi_window_size = getpagesize();
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}
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#endif
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memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr,
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"msi", msi_window_size);
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memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
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&sphb->msiwindow);
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pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
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pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
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pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
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pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
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@ -70,7 +70,7 @@ struct sPAPRPHBState {
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MemoryRegion memspace, iospace;
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MemoryRegion memspace, iospace;
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hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
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hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
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MemoryRegion memwindow, iowindow, msiwindow;
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MemoryRegion memwindow, iowindow;
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uint32_t dma_liobn;
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uint32_t dma_liobn;
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AddressSpace iommu_as;
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AddressSpace iommu_as;
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@ -13,6 +13,8 @@ struct sPAPRNVRAM;
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typedef struct sPAPREnvironment {
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typedef struct sPAPREnvironment {
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struct VIOsPAPRBus *vio_bus;
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struct VIOsPAPRBus *vio_bus;
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QLIST_HEAD(, sPAPRPHBState) phbs;
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QLIST_HEAD(, sPAPRPHBState) phbs;
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hwaddr msi_win_addr;
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MemoryRegion msiwindow;
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struct sPAPRNVRAM *nvram;
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struct sPAPRNVRAM *nvram;
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XICSState *icp;
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XICSState *icp;
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