linux-user: Save the correct resume address for MIPS signal handling
The current ISA mode needs to be saved in bit 0 of the resume address. If the current instruction happens to be in a branch delay slot, then the address of the preceding jump instruction should be stored instead. exception_resume_pc already does both of these tasks, so it is made available and reused. MIPS_HFLAG_BMASK in hflags is cleared, otherwise QEMU may treat the first instruction of the signal handler as a delay slot instruction. Signed-off-by: Kwok Cheung Yeung <kcy@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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			@ -2528,7 +2528,8 @@ setup_sigcontext(CPUMIPSState *regs, struct target_sigcontext *sc)
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    int err = 0;
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    int i;
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    err |= __put_user(regs->active_tc.PC, &sc->sc_pc);
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    err |= __put_user(exception_resume_pc(regs), &sc->sc_pc);
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    regs->hflags &= ~MIPS_HFLAG_BMASK;
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    __put_user(0, &sc->sc_regs[0]);
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    for (i = 1; i < 32; ++i) {
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			@ -668,6 +668,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
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hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
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		                               int rw);
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#endif
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target_ulong exception_resume_pc (CPUMIPSState *env);
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static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
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                                        target_ulong *cs_base, int *flags)
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			@ -366,8 +366,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
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    [EXCP_CACHE] = "cache error",
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};
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#if !defined(CONFIG_USER_ONLY)
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static target_ulong exception_resume_pc (CPUMIPSState *env)
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target_ulong exception_resume_pc (CPUMIPSState *env)
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{
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    target_ulong bad_pc;
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    target_ulong isa_mode;
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			@ -383,6 +382,7 @@ static target_ulong exception_resume_pc (CPUMIPSState *env)
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    return bad_pc;
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}
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#if !defined(CONFIG_USER_ONLY)
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static void set_hflags_for_handler (CPUMIPSState *env)
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{
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    /* Exception handlers are entered in 32-bit mode.  */
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