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target-arm: Add MDCR_EL2 

Add the MDCR_EL2 register. We don't implement any of
the debug-related traps this register controls yet, so
currently it simply reads back as written.

Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1444383794-16767-1-git-send-email-serge.fdrv@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked commit message; moved non-dummy definition from
debug_cp_reginfo to el2_cp_reginfo.]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Sergey Fedorov 2015-10-16 11:14:54 +01:00 committed by Peter Maydell
parent c209b05372
commit 14cc7b5437
2 changed files with 13 additions and 0 deletions
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1
target-arm/cpu.h
View File

@ -380,6 +380,7 @@ typedef struct CPUARMState {
uint64_t dbgwcr[16]; /* watchpoint control registers */ uint64_t dbgwcr[16]; /* watchpoint control registers */
uint64_t mdscr_el1; uint64_t mdscr_el1;
uint64_t oslsr_el1; /* OS Lock Status */ uint64_t oslsr_el1; /* OS Lock Status */
uint64_t mdcr_el2;
/* If the counter is enabled, this stores the last time the counter /* If the counter is enabled, this stores the last time the counter
* was reset. Otherwise it stores the counter value * was reset. Otherwise it stores the counter value
*/ */

12
target-arm/helper.c
View File

@ -3227,6 +3227,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
{ .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };
@ -3448,6 +3451,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.resetvalue = 0, .resetvalue = 0,
.writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
#endif #endif
/* The only field of MDCR_EL2 that has a defined architectural reset value
* is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
* don't impelment any PMU event counters, so using zero as a reset
* value for MDCR_EL2 is okay
*/
{ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
.access = PL2_RW, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };