prep: Add pc87312 Super I/O emulation
This provides floppy and IDE controllers as well as serial and parallel ports. However, dynamic configuration of devices is not yet supported. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> [AF: QOM'ify, split out header, create CharDriverState if absent] Signed-off-by: Andreas Färber <andreas.faerber@web.de>
This commit is contained in:
Hervé Poussineau
Andreas Färber
parent
acbb090b24
commit
1ae41f447d
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@ -39,6 +39,7 @@ hw-obj-$(CONFIG_I8259) += i8259_common.o i8259.o
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# PPC devices
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hw-obj-$(CONFIG_PREP_PCI) += prep_pci.o
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hw-obj-$(CONFIG_I82378) += i82378.o
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hw-obj-$(CONFIG_PC87312) += pc87312.o
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# Mac shared devices
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hw-obj-$(CONFIG_MACIO) += macio.o
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hw-obj-$(CONFIG_CUDA) += cuda.o
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@ -0,0 +1,386 @@
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/*
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* QEMU National Semiconductor PC87312 (Super I/O)
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*
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* Copyright (c) 2010-2012 Herve Poussineau
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* Copyright (c) 2011-2012 Andreas Färber
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "pc87312.h"
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#include "blockdev.h"
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#include "sysemu.h"
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#include "trace.h"
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#define REG_FER 0
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#define REG_FAR 1
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#define REG_PTR 2
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#define FER regs[REG_FER]
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#define FAR regs[REG_FAR]
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#define PTR regs[REG_PTR]
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#define FER_PARALLEL_EN 0x01
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#define FER_UART1_EN 0x02
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#define FER_UART2_EN 0x04
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#define FER_FDC_EN 0x08
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#define FER_FDC_4 0x10
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#define FER_FDC_ADDR 0x20
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#define FER_IDE_EN 0x40
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#define FER_IDE_ADDR 0x80
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#define FAR_PARALLEL_ADDR 0x03
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#define FAR_UART1_ADDR 0x0C
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#define FAR_UART2_ADDR 0x30
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#define FAR_UART_3_4 0xC0
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#define PTR_POWER_DOWN 0x01
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#define PTR_CLOCK_DOWN 0x02
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#define PTR_PWDN 0x04
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#define PTR_IRQ_5_7 0x08
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#define PTR_UART1_TEST 0x10
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#define PTR_UART2_TEST 0x20
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#define PTR_LOCK_CONF 0x40
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#define PTR_EPP_MODE 0x80
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/* Parallel port */
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static inline bool is_parallel_enabled(PC87312State *s)
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{
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return s->FER & FER_PARALLEL_EN;
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}
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static const uint32_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 };
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static inline uint32_t get_parallel_iobase(PC87312State *s)
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{
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return parallel_base[s->FAR & FAR_PARALLEL_ADDR];
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}
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static const uint32_t parallel_irq[] = { 5, 7, 5, 0 };
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static inline uint32_t get_parallel_irq(PC87312State *s)
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{
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int idx;
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idx = (s->FAR & FAR_PARALLEL_ADDR);
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if (idx == 0) {
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return (s->PTR & PTR_IRQ_5_7) ? 7 : 5;
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} else {
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return parallel_irq[idx];
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}
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}
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static inline bool is_parallel_epp(PC87312State *s)
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{
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return s->PTR & PTR_EPP_MODE;
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}
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/* UARTs */
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static const uint32_t uart_base[2][4] = {
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{ 0x3e8, 0x338, 0x2e8, 0x220 },
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{ 0x2e8, 0x238, 0x2e0, 0x228 }
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};
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static inline uint32_t get_uart_iobase(PC87312State *s, int i)
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{
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int idx;
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idx = (s->FAR >> (2 * i + 2)) & 0x3;
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if (idx == 0) {
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return 0x3f8;
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} else if (idx == 1) {
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return 0x2f8;
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} else {
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return uart_base[idx & 1][(s->FAR & FAR_UART_3_4) >> 6];
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}
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}
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static inline uint32_t get_uart_irq(PC87312State *s, int i)
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{
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int idx;
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idx = (s->FAR >> (2 * i + 2)) & 0x3;
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return (idx & 1) ? 3 : 4;
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}
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static inline bool is_uart_enabled(PC87312State *s, int i)
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{
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return s->FER & (FER_UART1_EN << i);
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}
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/* Floppy controller */
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static inline bool is_fdc_enabled(PC87312State *s)
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{
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return s->FER & FER_FDC_EN;
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}
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static inline uint32_t get_fdc_iobase(PC87312State *s)
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{
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return (s->FER & FER_FDC_ADDR) ? 0x370 : 0x3f0;
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}
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/* IDE controller */
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static inline bool is_ide_enabled(PC87312State *s)
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{
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return s->FER & FER_IDE_EN;
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}
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static inline uint32_t get_ide_iobase(PC87312State *s)
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{
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return (s->FER & FER_IDE_ADDR) ? 0x170 : 0x1f0;
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}
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static void reconfigure_devices(PC87312State *s)
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{
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error_report("pc87312: unsupported device reconfiguration (%02x %02x %02x)",
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s->FER, s->FAR, s->PTR);
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}
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static void pc87312_soft_reset(PC87312State *s)
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{
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static const uint8_t fer_init[] = {
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0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b,
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0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f,
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0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07,
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0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00,
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};
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static const uint8_t far_init[] = {
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0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01,
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0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24,
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0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24,
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0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10,
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};
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static const uint8_t ptr_init[] = {
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
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};
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s->read_id_step = 0;
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s->selected_index = REG_FER;
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s->FER = fer_init[s->config & 0x1f];
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s->FAR = far_init[s->config & 0x1f];
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s->PTR = ptr_init[s->config & 0x1f];
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}
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static void pc87312_hard_reset(PC87312State *s)
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{
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pc87312_soft_reset(s);
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}
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static void pc87312_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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PC87312State *s = opaque;
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trace_pc87312_io_write(addr, val);
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if ((addr & 1) == 0) {
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/* Index register */
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s->read_id_step = 2;
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s->selected_index = val;
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} else {
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/* Data register */
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if (s->selected_index < 3) {
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s->regs[s->selected_index] = val;
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reconfigure_devices(s);
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}
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}
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}
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static uint32_t pc87312_ioport_read(void *opaque, uint32_t addr)
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{
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PC87312State *s = opaque;
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uint32_t val;
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if ((addr & 1) == 0) {
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/* Index register */
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if (s->read_id_step++ == 0) {
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val = 0x88;
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} else if (s->read_id_step++ == 1) {
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val = 0;
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} else {
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val = s->selected_index;
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}
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} else {
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/* Data register */
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if (s->selected_index < 3) {
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val = s->regs[s->selected_index];
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} else {
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/* Invalid selected index */
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val = 0;
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}
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}
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trace_pc87312_io_read(addr, val);
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return val;
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}
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static int pc87312_post_load(void *opaque, int version_id)
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{
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PC87312State *s = opaque;
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reconfigure_devices(s);
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return 0;
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}
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static void pc87312_reset(DeviceState *d)
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{
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PC87312State *s = PC87312(d);
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pc87312_soft_reset(s);
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}
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static int pc87312_init(ISADevice *dev)
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{
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PC87312State *s;
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DeviceState *d;
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ISADevice *isa;
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ISABus *bus;
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CharDriverState *chr;
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DriveInfo *drive;
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char name[5];
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int i;
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s = PC87312(dev);
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bus = isa_bus_from_device(dev);
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pc87312_hard_reset(s);
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if (is_parallel_enabled(s)) {
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chr = parallel_hds[0];
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if (chr == NULL) {
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chr = qemu_chr_new("par0", "null", NULL);
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}
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isa = isa_create(bus, "isa-parallel");
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d = DEVICE(isa);
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qdev_prop_set_uint32(d, "index", 0);
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qdev_prop_set_uint32(d, "iobase", get_parallel_iobase(s));
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qdev_prop_set_uint32(d, "irq", get_parallel_irq(s));
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qdev_prop_set_chr(d, "chardev", chr);
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qdev_init_nofail(d);
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s->parallel.dev = isa;
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trace_pc87312_info_parallel(get_parallel_iobase(s),
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get_parallel_irq(s));
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}
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for (i = 0; i < 2; i++) {
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if (is_uart_enabled(s, i)) {
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chr = serial_hds[i];
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if (chr == NULL) {
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snprintf(name, sizeof(name), "ser%d", i);
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chr = qemu_chr_new(name, "null", NULL);
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}
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isa = isa_create(bus, "isa-serial");
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d = DEVICE(isa);
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qdev_prop_set_uint32(d, "index", i);
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qdev_prop_set_uint32(d, "iobase", get_uart_iobase(s, i));
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qdev_prop_set_uint32(d, "irq", get_uart_irq(s, i));
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qdev_prop_set_chr(d, "chardev", chr);
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qdev_init_nofail(d);
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s->uart[i].dev = isa;
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trace_pc87312_info_serial(i, get_uart_iobase(s, i),
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get_uart_irq(s, i));
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}
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}
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if (is_fdc_enabled(s)) {
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isa = isa_create(bus, "isa-fdc");
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d = DEVICE(isa);
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qdev_prop_set_uint32(d, "iobase", get_fdc_iobase(s));
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qdev_prop_set_uint32(d, "irq", 6);
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drive = drive_get(IF_FLOPPY, 0, 0);
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if (drive != NULL) {
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qdev_prop_set_drive_nofail(d, "driveA", drive->bdrv);
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}
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drive = drive_get(IF_FLOPPY, 0, 1);
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if (drive != NULL) {
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qdev_prop_set_drive_nofail(d, "driveB", drive->bdrv);
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}
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qdev_init_nofail(d);
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s->fdc.dev = isa;
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trace_pc87312_info_floppy(get_fdc_iobase(s));
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}
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if (is_ide_enabled(s)) {
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isa = isa_create(bus, "isa-ide");
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d = DEVICE(isa);
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qdev_prop_set_uint32(d, "iobase", get_ide_iobase(s));
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qdev_prop_set_uint32(d, "iobase2", get_ide_iobase(s) + 0x206);
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qdev_prop_set_uint32(d, "irq", 14);
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qdev_init_nofail(d);
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s->ide.dev = isa;
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trace_pc87312_info_ide(get_ide_iobase(s));
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}
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register_ioport_write(s->iobase, 2, 1, pc87312_ioport_write, s);
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register_ioport_read(s->iobase, 2, 1, pc87312_ioport_read, s);
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return 0;
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}
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static const VMStateDescription vmstate_pc87312 = {
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.name = "pc87312",
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = pc87312_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(read_id_step, PC87312State),
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VMSTATE_UINT8(selected_index, PC87312State),
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VMSTATE_UINT8_ARRAY(regs, PC87312State, 3),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property pc87312_properties[] = {
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DEFINE_PROP_HEX32("iobase", PC87312State, iobase, 0x398),
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DEFINE_PROP_UINT8("config", PC87312State, config, 1),
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DEFINE_PROP_END_OF_LIST()
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};
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static void pc87312_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
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ic->init = pc87312_init;
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dc->reset = pc87312_reset;
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dc->vmsd = &vmstate_pc87312;
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dc->props = pc87312_properties;
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}
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static const TypeInfo pc87312_type_info = {
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.name = TYPE_PC87312,
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(PC87312State),
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.class_init = pc87312_class_init,
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};
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static void pc87312_register_types(void)
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{
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type_register_static(&pc87312_type_info);
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}
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type_init(pc87312_register_types)
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@ -0,0 +1,66 @@
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/*
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* QEMU National Semiconductor PC87312 (Super I/O)
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*
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* Copyright (c) 2010-2012 Herve Poussineau
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* Copyright (c) 2011-2012 Andreas Färber
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*
|
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* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
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#ifndef QEMU_PC87312_H
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#define QEMU_PC87312_H
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#include "isa.h"
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#define TYPE_PC87312 "pc87312"
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#define PC87312(obj) OBJECT_CHECK(PC87312State, (obj), TYPE_PC87312)
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typedef struct PC87312State {
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ISADevice dev;
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uint32_t iobase;
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uint8_t config; /* initial configuration */
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struct {
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ISADevice *dev;
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} parallel;
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struct {
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ISADevice *dev;
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} uart[2];
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struct {
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||||
ISADevice *dev;
|
||||
BlockDriverState *drive[2];
|
||||
uint32_t base;
|
||||
} fdc;
|
||||
|
||||
struct {
|
||||
ISADevice *dev;
|
||||
uint32_t base;
|
||||
} ide;
|
||||
|
||||
uint8_t read_id_step;
|
||||
uint8_t selected_index;
|
||||
|
||||
uint8_t regs[3];
|
||||
} PC87312State;
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -694,6 +694,14 @@ mipsnet_read(uint64_t addr, uint32_t val) "read addr=0x%" PRIx64 " val=0x%x"
|
|||
mipsnet_write(uint64_t addr, uint64_t val) "write addr=0x%" PRIx64 " val=0x%" PRIx64 ""
|
||||
mipsnet_irq(uint32_t isr, uint32_t intctl) "set irq to %d (%02x)"
|
||||
|
||||
# hw/pc87312.c
|
||||
pc87312_io_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
|
||||
pc87312_io_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
|
||||
pc87312_info_floppy(uint32_t base) "base 0x%x"
|
||||
pc87312_info_ide(uint32_t base) "base 0x%x"
|
||||
pc87312_info_parallel(uint32_t base, uint32_t irq) "base 0x%x, irq %u"
|
||||
pc87312_info_serial(int n, uint32_t base, uint32_t irq) "id=%d, base 0x%x, irq %u"
|
||||
|
||||
# xen-all.c
|
||||
xen_ram_alloc(unsigned long ram_addr, unsigned long size) "requested: %#lx, size %#lx"
|
||||
xen_client_set_memory(uint64_t start_addr, unsigned long size, bool log_dirty) "%#"PRIx64" size %#lx, log_dirty %i"
|
||||
|
|
|
|||
Loading…
Reference in New Issue