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Update some comments, 64bit FPU support is functional regardless of 

funny non-standard fcr0 bits on earlier CPUs.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2919 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-06-01 21:57:32 +00:00
parent 8487327a1d
commit 1e3d0552f5
2 changed files with 8 additions and 5 deletions
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2
target-mips/TODO
View File

@ -16,7 +16,7 @@ General
MIPS64
------
- 64bit FPU enable flag not handled correctly
- Only lighly tested but apparently functional as of 2007-05-31.
"Generic" 4Kc system emulation
------------------------------

11
target-mips/translate_init.c
View File

@ -146,7 +146,7 @@ static mips_def_t mips_defs[] =
.SYNCI_Step = 16,
.CCRes = 2,
.Status_rw_bitmask = 0x3678FFFF,
/* XXX: The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
/* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
},
{
@ -176,7 +176,7 @@ static mips_def_t mips_defs[] =
.SYNCI_Step = 32,
.CCRes = 2,
.Status_rw_bitmask = 0x3678FFFF,
/* XXX: The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
.CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
(0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
},
@ -193,7 +193,7 @@ static mips_def_t mips_defs[] =
.SYNCI_Step = 32,
.CCRes = 2,
.Status_rw_bitmask = 0x36FBFFFF,
/* XXX: The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
.CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
(1 << FCR0_D) | (1 << FCR0_S) |
(0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
@ -279,6 +279,10 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
if (env->fcr0 & (1 << FCR0_F64))
env->hflags |= MIPS_HFLAG_F64;
#else
/* There are more full-featured MMU variants in older MIPS CPUs,
R3000, R6000 and R8000 come to mind. If we ever support them,
this check will need to look up a different place than those
newfangled config registers. */
switch ((env->CP0_Config0 >> CP0C0_MT) & 3) {
case 0:
no_mmu_init(env, def);
@ -290,7 +294,6 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
fixed_mmu_init(env, def);
break;
default:
/* Older CPUs like the R3000 may need nonstandard handling here. */
cpu_abort(env, "MMU type not supported\n");
}
env->CP0_Random = env->nb_tlb - 1;