Make SYNCI_Step and CCRes CPU-specific.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2651 c046a42c-6fe2-441c-8c8c-71466251a162
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			@ -5435,9 +5435,6 @@ void cpu_reset (CPUMIPSState *env)
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    env->hflags |= MIPS_HFLAG_UM;
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    env->user_mode_only = 1;
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#endif
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    /* XXX some guesswork here, values are CPU specific */
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    env->SYNCI_Step = 16;
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    env->CCRes = 2;
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}
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#include "translate_init.c"
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			@ -67,6 +67,8 @@ struct mips_def_t {
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    int32_t CP0_Config3;
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    int32_t CP0_Config6;
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    int32_t CP0_Config7;
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    int32_t SYNCI_Step;
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    int32_t CCRes;
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    int32_t CP1_fcr0;
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};
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			@ -82,6 +84,8 @@ static mips_def_t mips_defs[] =
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        .CP0_Config1 = MIPS_CONFIG1,
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        .CP0_Config2 = MIPS_CONFIG2,
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        .CP0_Config3 = MIPS_CONFIG3,
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        .SYNCI_Step = 32,
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        .CCRes = 2,
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        .CP1_fcr0 = MIPS_FCR0,
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    },
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    {
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			@ -91,6 +95,8 @@ static mips_def_t mips_defs[] =
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        .CP0_Config1 = MIPS_CONFIG1,
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        .CP0_Config2 = MIPS_CONFIG2,
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        .CP0_Config3 = MIPS_CONFIG3,
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        .SYNCI_Step = 32,
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        .CCRes = 2,
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        .CP1_fcr0 = MIPS_FCR0,
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    },
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    {
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			@ -100,6 +106,8 @@ static mips_def_t mips_defs[] =
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        .CP0_Config1 = MIPS_CONFIG1,
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        .CP0_Config2 = MIPS_CONFIG2,
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        .CP0_Config3 = MIPS_CONFIG3,
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        .SYNCI_Step = 32,
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        .CCRes = 2,
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        .CP1_fcr0 = MIPS_FCR0,
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    },
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    {
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			@ -109,6 +117,8 @@ static mips_def_t mips_defs[] =
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        .CP0_Config1 = MIPS_CONFIG1,
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        .CP0_Config2 = MIPS_CONFIG2,
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        .CP0_Config3 = MIPS_CONFIG3,
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        .SYNCI_Step = 32,
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        .CCRes = 2,
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        .CP1_fcr0 = MIPS_FCR0,
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    },
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    {
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			@ -118,6 +128,8 @@ static mips_def_t mips_defs[] =
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        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
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        .CP0_Config2 = MIPS_CONFIG2,
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        .CP0_Config3 = MIPS_CONFIG3,
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        .SYNCI_Step = 32,
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        .CCRes = 2,
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        .CP1_fcr0 = MIPS_FCR0,
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    },
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#else
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			@ -128,6 +140,8 @@ static mips_def_t mips_defs[] =
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        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
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        .CP0_Config2 = MIPS_CONFIG2,
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        .CP0_Config3 = MIPS_CONFIG3,
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        .SYNCI_Step = 16,
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        .CCRes = 2,
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        .CP1_fcr0 = MIPS_FCR0,
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    },
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#endif
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			@ -175,6 +189,8 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
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    env->CP0_Config3 = def->CP0_Config3;
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    env->CP0_Config6 = def->CP0_Config6;
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    env->CP0_Config7 = def->CP0_Config7;
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    env->SYNCI_Step = def->SYNCI_Step;
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    env->CCRes = def->CCRes;
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    env->fcr0 = def->CP1_fcr0;
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    return 0;
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}
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