tcg: Remove needless CPUState::current_tb
This field was used for telling cpu_interrupt() to unlink a chain of TBs being executed when it worked that way. Now, cpu_interrupt() don't do this anymore. So we don't need this field anymore. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedorov@linaro.org> Message-Id: <1462273462-14036-1-git-send-email-sergey.fedorov@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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			@ -68,7 +68,6 @@ void cpu_reloading_memory_map(void)
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void cpu_loop_exit(CPUState *cpu)
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{
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    cpu->current_tb = NULL;
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    siglongjmp(cpu->jmp_env, 1);
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}
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			@ -77,6 +76,5 @@ void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc)
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    if (pc) {
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        cpu_restore_state(cpu, pc);
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    }
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    cpu->current_tb = NULL;
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    siglongjmp(cpu->jmp_env, 1);
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}
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			@ -216,11 +216,9 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
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                         | (ignore_icount ? CF_IGNORE_ICOUNT : 0));
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    tb->orig_tb = cpu->tb_flushed ? NULL : orig_tb;
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    cpu->tb_flushed |= old_tb_flushed;
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    cpu->current_tb = tb;
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    /* execute the generated code */
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    trace_exec_tb_nocache(tb, tb->pc);
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    cpu_tb_exec(cpu, tb);
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    cpu->current_tb = NULL;
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    tb_phys_invalidate(tb, -1);
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    tb_free(tb);
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}
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			@ -532,9 +530,7 @@ int cpu_exec(CPUState *cpu)
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                    uintptr_t ret;
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                    trace_exec_tb(tb, tb->pc);
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                    /* execute the generated code */
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                    cpu->current_tb = tb;
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                    ret = cpu_tb_exec(cpu, tb);
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                    cpu->current_tb = NULL;
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                    last_tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK);
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                    tb_exit = ret & TB_EXIT_MASK;
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                    switch (tb_exit) {
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										13
									
								
								cputlb.c
								
								
								
								
							
							
						
						
									
										13
									
								
								cputlb.c
								
								
								
								
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			@ -76,10 +76,6 @@ void tlb_flush(CPUState *cpu, int flush_global)
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    tlb_debug("(%d)\n", flush_global);
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    /* must reset current TB so that interrupts cannot modify the
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       links while we are modifying them */
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    cpu->current_tb = NULL;
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    memset(env->tlb_table, -1, sizeof(env->tlb_table));
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    memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));
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    memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
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			@ -95,9 +91,6 @@ static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp)
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    CPUArchState *env = cpu->env_ptr;
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    tlb_debug("start\n");
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    /* must reset current TB so that interrupts cannot modify the
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       links while we are modifying them */
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    cpu->current_tb = NULL;
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    for (;;) {
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        int mmu_idx = va_arg(argp, int);
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			@ -152,9 +145,6 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
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        tlb_flush(cpu, 1);
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        return;
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    }
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    /* must reset current TB so that interrupts cannot modify the
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       links while we are modifying them */
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    cpu->current_tb = NULL;
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    addr &= TARGET_PAGE_MASK;
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    i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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			@ -193,9 +183,6 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
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        va_end(argp);
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        return;
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    }
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    /* must reset current TB so that interrupts cannot modify the
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       links while we are modifying them */
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    cpu->current_tb = NULL;
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    addr &= TARGET_PAGE_MASK;
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    i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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			@ -446,7 +446,6 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
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    resume_all_vcpus();
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    if (!kvm_enabled()) {
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        cs->current_tb = NULL;
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        tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1);
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        cpu_resume_from_signal(cs, NULL);
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    }
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			@ -253,7 +253,6 @@ struct kvm_run;
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 * @as: Pointer to the first AddressSpace, for the convenience of targets which
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 *      only have a single AddressSpace
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 * @env_ptr: Pointer to subclass-specific CPUArchState field.
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 * @current_tb: Currently executing TB.
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 * @gdb_regs: Additional GDB registers.
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 * @gdb_num_regs: Number of total registers accessible to GDB.
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 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
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			@ -305,7 +304,6 @@ struct CPUState {
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    MemoryRegion *memory;
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    void *env_ptr; /* CPUArchState */
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    struct TranslationBlock *current_tb;
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    struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
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    struct GDBRegisterState *gdb_regs;
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    int gdb_num_regs;
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			@ -254,7 +254,6 @@ static void cpu_common_reset(CPUState *cpu)
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    }
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    cpu->interrupt_request = 0;
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    cpu->current_tb = NULL;
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    cpu->halted = 0;
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    cpu->mem_io_pc = 0;
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    cpu->mem_io_vaddr = 0;
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			@ -305,7 +305,6 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
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        cpu_restore_state_from_tb(cpu, tb, retaddr);
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        if (tb->cflags & CF_NOCACHE) {
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            /* one-shot translation, invalidate it immediately */
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            cpu->current_tb = NULL;
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            tb_phys_invalidate(tb, -1);
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            tb_free(tb);
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        }
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			@ -1309,9 +1308,9 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end)
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void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
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                                   int is_cpu_write_access)
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{
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    TranslationBlock *tb, *tb_next, *saved_tb;
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    CPUState *cpu = current_cpu;
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    TranslationBlock *tb, *tb_next;
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#if defined(TARGET_HAS_PRECISE_SMC)
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    CPUState *cpu = current_cpu;
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    CPUArchState *env = NULL;
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#endif
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    tb_page_addr_t tb_start, tb_end;
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			@ -1378,20 +1377,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
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                                     ¤t_flags);
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            }
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#endif /* TARGET_HAS_PRECISE_SMC */
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            /* we need to do that to handle the case where a signal
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               occurs while doing tb_phys_invalidate() */
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            saved_tb = NULL;
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            if (cpu != NULL) {
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                saved_tb = cpu->current_tb;
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                cpu->current_tb = NULL;
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            }
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            tb_phys_invalidate(tb, -1);
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            if (cpu != NULL) {
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                cpu->current_tb = saved_tb;
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                if (cpu->interrupt_request && cpu->current_tb) {
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                    cpu_interrupt(cpu, cpu->interrupt_request);
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                }
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            }
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        }
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        tb = tb_next;
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    }
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			@ -1407,7 +1393,6 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
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        /* we generate a block containing just the instruction
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           modifying the memory. It will ensure that it cannot modify
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           itself */
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        cpu->current_tb = NULL;
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        tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
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        cpu_resume_from_signal(cpu, NULL);
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    }
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			@ -1512,7 +1497,6 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
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        /* we generate a block containing just the instruction
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           modifying the memory. It will ensure that it cannot modify
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           itself */
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        cpu->current_tb = NULL;
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        tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
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        if (locked) {
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            mmap_unlock();
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