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target-mips: fix wrong microMIPS opcode encoding 

While reading microMIPS decoding, I found a possible wrong opcode
encoding. According to [1] page 166, the bits 13..12 for MULTU is
0x01 rather than 0x00. Please review, thanks.

[1] MIPS Architecture for Programmers VolumeIV-e: The MIPS DSP
    Application-Specific Extension to the microMIPS32 Architecture

Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
(cherry picked from commit 6801038bc5)

Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
This commit is contained in:
陳韋任 (Wei-Ren Chen) 2012-11-14 10:49:55 +08:00 committed by Michael Roth
parent f6b803df74
commit 357414daa4
1 changed files with 1 additions and 1 deletions
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target-mips/translate.c
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@ -9486,7 +9486,7 @@ enum {
/* bits 13..12 for 0x32 */
MULT_ACC = 0x0,
MULTU_ACC = 0x0,
MULTU_ACC = 0x1,
/* bits 15..12 for 0x2c */
SEB = 0x2,