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target-alpha: Implement TLB flush primitives. 

Expose these via MTPR, more or less like the real HW does.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2011-04-18 20:01:20 -07:00 committed by Richard Henderson
parent e5214853ea
commit 3b4fefd6e6
3 changed files with 34 additions and 12 deletions
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3
target-alpha/helper.h
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@ -110,6 +110,9 @@ DEF_HELPER_2(stl_phys, void, i64, i64)
DEF_HELPER_2(stq_phys, void, i64, i64) DEF_HELPER_2(stq_phys, void, i64, i64)
DEF_HELPER_2(stl_c_phys, i64, i64, i64) DEF_HELPER_2(stl_c_phys, i64, i64, i64)
DEF_HELPER_2(stq_c_phys, i64, i64, i64) DEF_HELPER_2(stq_c_phys, i64, i64, i64)
DEF_HELPER_FLAGS_0(tbia, TCG_CALL_CONST, void)
DEF_HELPER_FLAGS_1(tbis, TCG_CALL_CONST, void, i64)
#endif #endif
#include "def-helper.h" #include "def-helper.h"

11
target-alpha/op_helper.c
View File

@ -1205,6 +1205,16 @@ void helper_hw_ret (uint64_t a)
swap_shadow_regs(env); swap_shadow_regs(env);
} }
} }
void helper_tbia(void)
{
tlb_flush(env, 1);
}
void helper_tbis(uint64_t p)
{
tlb_flush_page(env, p);
}
#endif #endif
/*****************************************************************************/ /*****************************************************************************/
@ -1335,5 +1345,4 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
} }
env = saved_env; env = saved_env;
} }
#endif #endif

32
target-alpha/translate.c
View File

@ -1621,7 +1621,6 @@ static void gen_mfpr(int ra, int regno)
static void gen_mtpr(int rb, int regno) static void gen_mtpr(int rb, int regno)
{ {
TCGv tmp; TCGv tmp;
int data;
if (rb == 31) { if (rb == 31) {
tmp = tcg_const_i64(0); tmp = tcg_const_i64(0);
@ -1629,16 +1628,27 @@ static void gen_mtpr(int rb, int regno)
tmp = cpu_ir[rb]; tmp = cpu_ir[rb];
} }
/* The basic registers are data only, and unknown registers /* These two register numbers perform a TLB cache flush. Thankfully we
are read-zero, write-ignore. */ can only do this inside PALmode, which means that the current basic
data = cpu_pr_data(regno); block cannot be affected by the change in mappings. */
if (data != 0) { if (regno == 255) {
if (data & PR_BYTE) { /* TBIA */
tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); gen_helper_tbia();
} else if (data & PR_LONG) { } else if (regno == 254) {
tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG); /* TBIS */
} else { gen_helper_tbis(tmp);
tcg_gen_st_i64(tmp, cpu_env, data); } else {
/* The basic registers are data only, and unknown registers
are read-zero, write-ignore. */
int data = cpu_pr_data(regno);
if (data != 0) {
if (data & PR_BYTE) {
tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE);
} else if (data & PR_LONG) {
tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG);
} else {
tcg_gen_st_i64(tmp, cpu_env, data);
}
} }
} }