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ppc: pnv: drop PnvChipClass::cpu_model field 

deduce core type directly from chip type instead of
maintaining type mapping in PnvChipClass::cpu_model.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Igor Mammedov 2017-10-09 21:51:10 +02:00 committed by David Gibson
parent 7383af1edc
commit 40abf43f72
4 changed files with 13 additions and 19 deletions
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25
hw/ppc/pnv.c
View File

@ -55,6 +55,16 @@
#define KERNEL_LOAD_ADDR 0x20000000
#define INITRD_LOAD_ADDR 0x40000000
static const char *pnv_chip_core_typename(const PnvChip *o)
{
const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
const char *core_type = object_class_get_name(object_class_by_name(s));
g_free(s);
return core_type;
}
/*
* On Power Systems E880 (POWER8), the max cpus (threads) should be :
* 4 * 4 sockets * 12 cores * 8 threads = 1536
@ -269,8 +279,7 @@ static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt)
static void powernv_populate_chip(PnvChip *chip, void *fdt)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
char *typename = pnv_core_typename(pcc->cpu_model);
const char *typename = pnv_chip_core_typename(chip);
size_t typesize = object_type_get_instance_size(typename);
int i;
@ -300,7 +309,6 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt)
powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start,
chip->ram_size);
}
g_free(typename);
}
static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off)
@ -712,7 +720,6 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvChipClass *k = PNV_CHIP_CLASS(klass);
k->cpu_model = "power8e_v2.1";
k->chip_type = PNV_CHIP_POWER8E;
k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
k->cores_mask = POWER8E_CORE_MASK;
@ -734,7 +741,6 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvChipClass *k = PNV_CHIP_CLASS(klass);
k->cpu_model = "power8_v2.0";
k->chip_type = PNV_CHIP_POWER8;
k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
k->cores_mask = POWER8_CORE_MASK;
@ -756,7 +762,6 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvChipClass *k = PNV_CHIP_CLASS(klass);
k->cpu_model = "power8nvl_v1.0";
k->chip_type = PNV_CHIP_POWER8NVL;
k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
k->cores_mask = POWER8_CORE_MASK;
@ -778,7 +783,6 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvChipClass *k = PNV_CHIP_CLASS(klass);
k->cpu_model = "power9_v2.0";
k->chip_type = PNV_CHIP_POWER9;
k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
k->cores_mask = POWER9_CORE_MASK;
@ -853,7 +857,7 @@ static void pnv_chip_init(Object *obj)
static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
char *typename = pnv_core_typename(pcc->cpu_model);
const char *typename = pnv_chip_core_typename(chip);
size_t typesize = object_type_get_instance_size(typename);
int i, j;
char *name;
@ -878,8 +882,6 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->mmio);
}
}
g_free(typename);
}
static void pnv_chip_realize(DeviceState *dev, Error **errp)
@ -887,7 +889,7 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
PnvChip *chip = PNV_CHIP(dev);
Error *error = NULL;
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
char *typename = pnv_core_typename(pcc->cpu_model);
const char *typename = pnv_chip_core_typename(chip);
size_t typesize = object_type_get_instance_size(typename);
int i, core_hwid;
@ -946,7 +948,6 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
&PNV_CORE(pnv_core)->xscom_regs);
i++;
}
g_free(typename);
/* Create LPC controller */
object_property_set_bool(OBJECT(&chip->lpc), true, "realized",

5
hw/ppc/pnv_core.c
View File

@ -246,9 +246,4 @@ static const TypeInfo pnv_core_infos[] = {
DEFINE_PNV_CORE_TYPE("power9_v2.0"),
};
char *pnv_core_typename(const char *model)
{
return g_strdup_printf(PNV_CORE_TYPE_NAME("%s"), model);
}
DEFINE_TYPES(pnv_core_infos)

1
include/hw/ppc/pnv.h
View File

@ -69,7 +69,6 @@ typedef struct PnvChipClass {
SysBusDeviceClass parent_class;
/*< public >*/
const char *cpu_model;
PnvChipType chip_type;
uint64_t chip_cfam_id;
uint64_t cores_mask;

1
include/hw/ppc/pnv_core.h
View File

@ -46,6 +46,5 @@ typedef struct PnvCoreClass {
#define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
#define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX
extern char *pnv_core_typename(const char *model);
#endif /* _PPC_PNV_CORE_H */