falso
/
qemu-irix
mirror of https://github.com/n64decomp/qemu-irix.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target-arm: Allow 3reg_wide undefreq to encode more bad size options 

The current undefreq field in the neon_3reg_wide handling allows us
to encode "UNDEF if size != 0" and "UNDEF if size == 0". This is
no longer sufficient with the advent of 64-bit polynomial VMULL,
which means we want to UNDEF if size == 1. Change the undefreq
encoding to use separate bits for all of "UNDEF if size == 0",
"UNDEF if size == 1" and "UNDEF if size == 2".

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401386724-26529-3-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2014-06-09 15:43:23 +01:00
parent f1ecb913d8
commit 526d0096e5
1 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
target-arm/translate.c
View File

@ -5954,10 +5954,11 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
int src1_wide; int src1_wide;
int src2_wide; int src2_wide;
int prewiden; int prewiden;
/* undefreq: bit 0 : UNDEF if size != 0 /* undefreq: bit 0 : UNDEF if size == 0
* bit 1 : UNDEF if size == 0 * bit 1 : UNDEF if size == 1
* bit 2 : UNDEF if U == 1 * bit 2 : UNDEF if size == 2
* Note that [1:0] set implies 'always UNDEF' * bit 3 : UNDEF if U == 1
* Note that [2:0] set implies 'always UNDEF'
*/ */
int undefreq; int undefreq;
/* prewiden, src1_wide, src2_wide, undefreq */ /* prewiden, src1_wide, src2_wide, undefreq */
@ -5971,13 +5972,13 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
{0, 1, 1, 0}, /* VSUBHN */ {0, 1, 1, 0}, /* VSUBHN */
{0, 0, 0, 0}, /* VABDL */ {0, 0, 0, 0}, /* VABDL */
{0, 0, 0, 0}, /* VMLAL */ {0, 0, 0, 0}, /* VMLAL */
{0, 0, 0, 6}, /* VQDMLAL */ {0, 0, 0, 9}, /* VQDMLAL */
{0, 0, 0, 0}, /* VMLSL */ {0, 0, 0, 0}, /* VMLSL */
{0, 0, 0, 6}, /* VQDMLSL */ {0, 0, 0, 9}, /* VQDMLSL */
{0, 0, 0, 0}, /* Integer VMULL */ {0, 0, 0, 0}, /* Integer VMULL */
{0, 0, 0, 2}, /* VQDMULL */ {0, 0, 0, 1}, /* VQDMULL */
{0, 0, 0, 5}, /* Polynomial VMULL */ {0, 0, 0, 15}, /* Polynomial VMULL */
{0, 0, 0, 3}, /* Reserved: always UNDEF */ {0, 0, 0, 7}, /* Reserved: always UNDEF */
}; };
prewiden = neon_3reg_wide[op][0]; prewiden = neon_3reg_wide[op][0];
@ -5985,9 +5986,8 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
src2_wide = neon_3reg_wide[op][2]; src2_wide = neon_3reg_wide[op][2];
undefreq = neon_3reg_wide[op][3]; undefreq = neon_3reg_wide[op][3];
if (((undefreq & 1) && (size != 0)) || if ((undefreq & (1 << size)) ||
((undefreq & 2) && (size == 0)) || ((undefreq & 8) && u)) {
((undefreq & 4) && u)) {
return 1; return 1;
} }
if ((src1_wide && (rn & 1)) || if ((src1_wide && (rn & 1)) ||