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i.MX: Standardize i.MX GPIO debug 

The goal is to have debug code always compiled during build.

We standardize all debug output on the following format:

[QOM_TYPE_NAME]reporting_function: debug message

The qemu_log_mask() outputis following the same format as
the above debug.

Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 4f2007adcf0f579864bb4dd8a825824e0e9098b8.1445781957.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jean-Christophe Dubois 2015-10-25 15:16:11 +01:00 committed by Peter Maydell
parent 8ccce77c04
commit 5641112574
1 changed files with 14 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
hw/gpio/imx_gpio.c
View File

@ -29,11 +29,12 @@ typedef enum IMXGPIOLevel {
} IMXGPIOLevel; } IMXGPIOLevel;
#define DPRINTF(fmt, args...) \ #define DPRINTF(fmt, args...) \
do { \ do { \
if (DEBUG_IMX_GPIO) { \ if (DEBUG_IMX_GPIO) { \
fprintf(stderr, "%s: " fmt , __func__, ##args); \ fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPIO, \
} \ __func__, ##args); \
} while (0) } \
} while (0)
static const char *imx_gpio_reg_name(uint32_t reg) static const char *imx_gpio_reg_name(uint32_t reg)
{ {
@ -176,19 +177,19 @@ static uint64_t imx_gpio_read(void *opaque, hwaddr offset, unsigned size)
if (s->has_edge_sel) { if (s->has_edge_sel) {
reg_value = s->edge_sel; reg_value = s->edge_sel;
} else { } else {
qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: EDGE_SEL register not " qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
"present on this version of GPIO device\n", "present on this version of GPIO device\n",
TYPE_IMX_GPIO, __func__); TYPE_IMX_GPIO, __func__);
} }
break; break;
default: default:
qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad register at offset %d\n", qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
TYPE_IMX_GPIO, __func__, (int)offset); HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
break; break;
} }
DPRINTF("(%s) = 0x%"PRIx32"\n", imx_gpio_reg_name(offset), reg_value); DPRINTF("(%s) = 0x%" PRIx32 "\n", imx_gpio_reg_name(offset), reg_value);
return reg_value; return reg_value;
} }
@ -198,7 +199,7 @@ static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
{ {
IMXGPIOState *s = IMX_GPIO(opaque); IMXGPIOState *s = IMX_GPIO(opaque);
DPRINTF("(%s, value = 0x%"PRIx32")\n", imx_gpio_reg_name(offset), DPRINTF("(%s, value = 0x%" PRIx32 ")\n", imx_gpio_reg_name(offset),
(uint32_t)value); (uint32_t)value);
switch (offset) { switch (offset) {
@ -238,15 +239,15 @@ static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
s->edge_sel = value; s->edge_sel = value;
imx_gpio_set_all_int_lines(s); imx_gpio_set_all_int_lines(s);
} else { } else {
qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: EDGE_SEL register not " qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
"present on this version of GPIO device\n", "present on this version of GPIO device\n",
TYPE_IMX_GPIO, __func__); TYPE_IMX_GPIO, __func__);
} }
break; break;
default: default:
qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad register at offset %d\n", qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
TYPE_IMX_GPIO, __func__, (int)offset); HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
break; break;
} }