falso
/
qemu-irix
mirror of https://github.com/n64decomp/qemu-irix.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target-arm: make arm_current_el() return EL3 

Make arm_current_el() return EL3 for secure PL1 and monitor mode.
Increase MMU modes since mmu_index is directly inferred from arm_
current_el(). Change assertion in arm_el_is_aa64() to allow EL3.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1413910544-20150-6-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Fabian Aggeler 2014-10-24 12:19:14 +01:00 committed by Peter Maydell
parent dcbff19bd0
commit 592125f83a
1 changed files with 20 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
target-arm/cpu.h
View File

@ -100,7 +100,7 @@ typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
struct arm_boot_info; struct arm_boot_info;
#define NB_MMU_MODES 2 #define NB_MMU_MODES 4
/* We currently assume float and double are IEEE single and double /* We currently assume float and double are IEEE single and double
precision respectively. precision respectively.
@ -803,11 +803,12 @@ static inline bool arm_is_secure(CPUARMState *env)
/* Return true if the specified exception level is running in AArch64 state. */ /* Return true if the specified exception level is running in AArch64 state. */
static inline bool arm_el_is_aa64(CPUARMState *env, int el) static inline bool arm_el_is_aa64(CPUARMState *env, int el)
{ {
/* We don't currently support EL2 or EL3, and this isn't valid for EL0 /* We don't currently support EL2, and this isn't valid for EL0
* (if we're in EL0, is_a64() is what you want, and if we're not in EL0 * (if we're in EL0, is_a64() is what you want, and if we're not in EL0
* then the state of EL0 isn't well defined.) * then the state of EL0 isn't well defined.)
*/ */
assert(el == 1); assert(el == 1 || el == 3);
/* AArch64-capable CPUs always run with EL1 in AArch64 mode. This /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
* is a QEMU-imposed simplification which we may wish to change later. * is a QEMU-imposed simplification which we may wish to change later.
* If we in future support EL2 and/or EL3, then the state of lower * If we in future support EL2 and/or EL3, then the state of lower
@ -996,17 +997,27 @@ static inline bool cptype_valid(int cptype)
*/ */
static inline int arm_current_el(CPUARMState *env) static inline int arm_current_el(CPUARMState *env)
{ {
if (env->aarch64) { if (is_a64(env)) {
return extract32(env->pstate, 2, 2); return extract32(env->pstate, 2, 2);
} }
if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { switch (env->uncached_cpsr & 0x1f) {
case ARM_CPU_MODE_USR:
return 0; return 0;
case ARM_CPU_MODE_HYP:
return 2;
case ARM_CPU_MODE_MON:
return 3;
default:
if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
/* If EL3 is 32-bit then all secure privileged modes run in
* EL3
*/
return 3;
}
return 1;
} }
/* We don't currently implement the Virtualization or TrustZone
* extensions, so EL2 and EL3 don't exist for us.
*/
return 1;
} }
typedef struct ARMCPRegInfo ARMCPRegInfo; typedef struct ARMCPRegInfo ARMCPRegInfo;