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target-microblaze: Convert use-mmu to a CPU property 

Originally the use-mmu PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Alistair Francis 2015-06-18 21:16:29 -07:00 committed by Edgar E. Iglesias
parent be67e9ab97
commit 7144612370
4 changed files with 6 additions and 4 deletions
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1
target-microblaze/cpu-qom.h
View File

@ -64,6 +64,7 @@ typedef struct MicroBlazeCPU {
bool stackprot; bool stackprot;
uint32_t base_vectors; uint32_t base_vectors;
uint8_t use_fpu; uint8_t use_fpu;
bool use_mmu;
} cfg; } cfg;
CPUMBState env; CPUMBState env;

5
target-microblaze/cpu.c
View File

@ -98,7 +98,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
| PVR0_USE_EXC_MASK \ | PVR0_USE_EXC_MASK \
| PVR0_USE_ICACHE_MASK \ | PVR0_USE_ICACHE_MASK \
| PVR0_USE_DCACHE_MASK \ | PVR0_USE_DCACHE_MASK \
| PVR0_USE_MMU \
| (0xb << 8); | (0xb << 8);
env->pvr.regs[2] = PVR2_D_OPB_MASK \ env->pvr.regs[2] = PVR2_D_OPB_MASK \
| PVR2_D_LMB_MASK \ | PVR2_D_LMB_MASK \
@ -114,7 +113,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
| 0; | 0;
env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
(cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0); (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0); (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
@ -168,6 +168,7 @@ static Property mb_properties[] = {
* are enabled * are enabled
*/ */
DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };

2
target-microblaze/cpu.h
View File

@ -122,7 +122,7 @@ typedef struct CPUMBState CPUMBState;
#define PVR0_USE_EXC_MASK 0x04000000 #define PVR0_USE_EXC_MASK 0x04000000
#define PVR0_USE_ICACHE_MASK 0x02000000 #define PVR0_USE_ICACHE_MASK 0x02000000
#define PVR0_USE_DCACHE_MASK 0x01000000 #define PVR0_USE_DCACHE_MASK 0x01000000
#define PVR0_USE_MMU 0x00800000 /* new */ #define PVR0_USE_MMU_MASK 0x00800000
#define PVR0_USE_BTC 0x00400000 #define PVR0_USE_BTC 0x00400000
#define PVR0_ENDI 0x00200000 #define PVR0_ENDI 0x00200000
#define PVR0_FAULT 0x00100000 #define PVR0_FAULT 0x00100000

2
target-microblaze/helper.c
View File

@ -56,7 +56,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int prot; int prot;
mmu_available = 0; mmu_available = 0;
if (env->pvr.regs[0] & PVR0_USE_MMU) { if (cpu->cfg.use_mmu) {
mmu_available = 1; mmu_available = 1;
if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK) if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
&& (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) { && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {