falso
/
qemu-irix
mirror of https://github.com/n64decomp/qemu-irix.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

arm_gic: convert to memory API 

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2011-08-15 17:17:17 +03:00 committed by Anthony Liguori
parent 312b4234c6
commit 755c080225
4 changed files with 44 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
hw/arm_gic.c
View File

@ -104,7 +104,7 @@ typedef struct gic_state
int num_cpu; int num_cpu;
#endif #endif
int iomemtype; MemoryRegion iomem;
} gic_state; } gic_state;
/* TODO: Many places that call this routine could be optimized. */ /* TODO: Many places that call this routine could be optimized. */
@ -567,16 +567,12 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
gic_dist_writew(opaque, offset + 2, value >> 16); gic_dist_writew(opaque, offset + 2, value >> 16);
} }
static CPUReadMemoryFunc * const gic_dist_readfn[] = { static const MemoryRegionOps gic_dist_ops = {
gic_dist_readb, .old_mmio = {
gic_dist_readw, .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, },
gic_dist_readl .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, },
}; },
.endianness = DEVICE_NATIVE_ENDIAN,
static CPUWriteMemoryFunc * const gic_dist_writefn[] = {
gic_dist_writeb,
gic_dist_writew,
gic_dist_writel
}; };
#ifndef NVIC #ifndef NVIC
@ -741,9 +737,7 @@ static void gic_init(gic_state *s)
for (i = 0; i < NUM_CPU(s); i++) { for (i = 0; i < NUM_CPU(s); i++) {
sysbus_init_irq(&s->busdev, &s->parent_irq[i]); sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
} }
s->iomemtype = cpu_register_io_memory(gic_dist_readfn, memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
gic_dist_writefn, s,
DEVICE_NATIVE_ENDIAN);
gic_reset(s); gic_reset(s);
register_savevm(NULL, "arm_gic", -1, 1, gic_save, gic_load, s); register_savevm(NULL, "arm_gic", -1, 1, gic_save, gic_load, s);
} }

3
hw/armv7m_nvic.c
View File

@ -13,6 +13,7 @@
#include "sysbus.h" #include "sysbus.h"
#include "qemu-timer.h" #include "qemu-timer.h"
#include "arm-misc.h" #include "arm-misc.h"
#include "exec-memory.h"
/* 32 internal lines (16 used for system exceptions) plus 64 external /* 32 internal lines (16 used for system exceptions) plus 64 external
interrupt lines. */ interrupt lines. */
@ -384,7 +385,7 @@ static int armv7m_nvic_init(SysBusDevice *dev)
nvic_state *s= FROM_SYSBUSGIC(nvic_state, dev); nvic_state *s= FROM_SYSBUSGIC(nvic_state, dev);
gic_init(&s->gic); gic_init(&s->gic);
cpu_register_physical_memory(0xe000e000, 0x1000, s->gic.iomemtype); memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->gic.iomem);
s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s); s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
vmstate_register(&dev->qdev, -1, &vmstate_nvic, s); vmstate_register(&dev->qdev, -1, &vmstate_nvic, s);
return 0; return 0;

37
hw/mpcore.c
View File

@ -40,6 +40,8 @@ typedef struct mpcore_priv_state {
int iomemtype; int iomemtype;
mpcore_timer_state timer[8]; mpcore_timer_state timer[8];
uint32_t num_cpu; uint32_t num_cpu;
MemoryRegion iomem;
MemoryRegion container;
} mpcore_priv_state; } mpcore_priv_state;
/* Per-CPU Timers. */ /* Per-CPU Timers. */
@ -151,7 +153,8 @@ static void mpcore_timer_init(mpcore_priv_state *mpcore,
/* Per-CPU private memory mapped IO. */ /* Per-CPU private memory mapped IO. */
static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset) static uint64_t mpcore_priv_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{ {
mpcore_priv_state *s = (mpcore_priv_state *)opaque; mpcore_priv_state *s = (mpcore_priv_state *)opaque;
int id; int id;
@ -203,7 +206,7 @@ bad_reg:
} }
static void mpcore_priv_write(void *opaque, target_phys_addr_t offset, static void mpcore_priv_write(void *opaque, target_phys_addr_t offset,
uint32_t value) uint64_t value, unsigned size)
{ {
mpcore_priv_state *s = (mpcore_priv_state *)opaque; mpcore_priv_state *s = (mpcore_priv_state *)opaque;
int id; int id;
@ -250,23 +253,19 @@ bad_reg:
hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
} }
static CPUReadMemoryFunc * const mpcore_priv_readfn[] = { static const MemoryRegionOps mpcore_priv_ops = {
mpcore_priv_read, .read = mpcore_priv_read,
mpcore_priv_read, .write = mpcore_priv_write,
mpcore_priv_read .endianness = DEVICE_NATIVE_ENDIAN,
}; };
static CPUWriteMemoryFunc * const mpcore_priv_writefn[] = { static void mpcore_priv_map_setup(mpcore_priv_state *s)
mpcore_priv_write,
mpcore_priv_write,
mpcore_priv_write
};
static void mpcore_priv_map(SysBusDevice *dev, target_phys_addr_t base)
{ {
mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev); memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
cpu_register_physical_memory(base, 0x1000, s->iomemtype); memory_region_init_io(&s->iomem, &mpcore_priv_ops, s, "mpcode-priv",
cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype); 0x1000);
memory_region_add_subregion(&s->container, 0, &s->iomem);
memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
} }
static int mpcore_priv_init(SysBusDevice *dev) static int mpcore_priv_init(SysBusDevice *dev)
@ -275,10 +274,8 @@ static int mpcore_priv_init(SysBusDevice *dev)
int i; int i;
gic_init(&s->gic, s->num_cpu); gic_init(&s->gic, s->num_cpu);
s->iomemtype = cpu_register_io_memory(mpcore_priv_readfn, mpcore_priv_map_setup(s);
mpcore_priv_writefn, s, sysbus_init_mmio_region(dev, &s->container);
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio_cb(dev, 0x2000, mpcore_priv_map);
for (i = 0; i < s->num_cpu * 2; i++) { for (i = 0; i < s->num_cpu * 2; i++) {
mpcore_timer_init(s, &s->timer[i], i); mpcore_timer_init(s, &s->timer[i], i);
} }

38
hw/realview_gic.c
View File

@ -23,39 +23,37 @@ gic_get_current_cpu(void)
typedef struct { typedef struct {
gic_state gic; gic_state gic;
int iomemtype; MemoryRegion iomem;
MemoryRegion container;
} RealViewGICState; } RealViewGICState;
static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset) static uint64_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{ {
gic_state *s = (gic_state *)opaque; gic_state *s = (gic_state *)opaque;
return gic_cpu_read(s, gic_get_current_cpu(), offset); return gic_cpu_read(s, gic_get_current_cpu(), offset);
} }
static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset, static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset,
uint32_t value) uint64_t value, unsigned size)
{ {
gic_state *s = (gic_state *)opaque; gic_state *s = (gic_state *)opaque;
gic_cpu_write(s, gic_get_current_cpu(), offset, value); gic_cpu_write(s, gic_get_current_cpu(), offset, value);
} }
static CPUReadMemoryFunc * const realview_gic_cpu_readfn[] = { static const MemoryRegionOps realview_gic_cpu_ops = {
realview_gic_cpu_read, .read = realview_gic_cpu_read,
realview_gic_cpu_read, .write = realview_gic_cpu_write,
realview_gic_cpu_read .endianness = DEVICE_NATIVE_ENDIAN,
}; };
static CPUWriteMemoryFunc * const realview_gic_cpu_writefn[] = { static void realview_gic_map_setup(RealViewGICState *s)
realview_gic_cpu_write,
realview_gic_cpu_write,
realview_gic_cpu_write
};
static void realview_gic_map(SysBusDevice *dev, target_phys_addr_t base)
{ {
RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev); memory_region_init(&s->container, "realview-gic-container", 0x2000);
cpu_register_physical_memory(base, 0x1000, s->iomemtype); memory_region_init_io(&s->iomem, &realview_gic_cpu_ops, &s->gic,
cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype); "realview-gic", 0x1000);
memory_region_add_subregion(&s->container, 0, &s->iomem);
memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
} }
static int realview_gic_init(SysBusDevice *dev) static int realview_gic_init(SysBusDevice *dev)
@ -63,10 +61,8 @@ static int realview_gic_init(SysBusDevice *dev)
RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev); RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
gic_init(&s->gic); gic_init(&s->gic);
s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn, realview_gic_map_setup(s);
realview_gic_cpu_writefn, s, sysbus_init_mmio_region(dev, &s->container);
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map);
return 0; return 0;
} }