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xilinx_timer: Fix writes into TCSR register 

The TCSR register has only 11 valid bits. This is now used by the
linux kernel to auto-detect endianness, and causes Linux 3.15-rc1
and later to hang when run under qemu-microblaze. Mask valid bits
before writing the register to solve the problem.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Guenter Roeck 2014-04-25 08:39:48 -07:00 committed by Edgar E. Iglesias
parent 12f7fb6086
commit 7dfba6dfbf
1 changed files with 1 additions and 1 deletions
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2
hw/timer/xilinx_timer.c
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@ -169,7 +169,7 @@ timer_write(void *opaque, hwaddr addr,
if (value & TCSR_TINT)
value &= ~TCSR_TINT;
xt->regs[addr] = value;
xt->regs[addr] = value & 0x7ff;
if (value & TCSR_ENT)
timer_enable(xt);
break;