target-ppc: Introduce DFP Shift Significand
Add emulation of the PowerPC Decimal Floating Point Shift Significand Left Immediate (dscli[q][.]) and DFP Shift Significant Right Immediate (dscri[q][.]) instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Tom Musta
Alexander Graf
parent
297666eba0
commit
804e654a56
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@ -1220,3 +1220,98 @@ void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *a, uint64_t *b) \
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DFP_HELPER_IEX(diex, 64)
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DFP_HELPER_IEX(diex, 64)
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DFP_HELPER_IEX(diexq, 128)
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DFP_HELPER_IEX(diexq, 128)
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static void dfp_clear_lmd_from_g5msb(uint64_t *t)
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{
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/* The most significant 5 bits of the PowerPC DFP format combine bits */
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/* from the left-most decimal digit (LMD) and the biased exponent. */
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/* This routine clears the LMD bits while preserving the exponent */
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/* bits. See "Figure 80: Encoding of bits 0:4 of the G field for */
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/* Finite Numbers" in the Power ISA for additional details. */
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uint64_t g5msb = (*t >> 58) & 0x1F;
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if ((g5msb >> 3) < 3) { /* LMD in [0-7] ? */
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*t &= ~(7ULL << 58);
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} else {
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switch (g5msb & 7) {
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case 0:
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case 1:
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g5msb = 0;
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break;
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case 2:
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case 3:
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g5msb = 0x8;
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break;
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case 4:
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case 5:
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g5msb = 0x10;
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break;
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case 6:
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g5msb = 0x1E;
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break;
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case 7:
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g5msb = 0x1F;
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break;
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}
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*t &= ~(0x1fULL << 58);
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*t |= (g5msb << 58);
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}
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}
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#define DFP_HELPER_SHIFT(op, size, shift_left) \
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void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *a, \
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uint32_t sh) \
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{ \
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struct PPC_DFP dfp; \
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unsigned max_digits = ((size) == 64) ? 16 : 34; \
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\
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dfp_prepare_decimal##size(&dfp, a, 0, env); \
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\
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if (sh <= max_digits) { \
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\
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decNumber shd; \
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unsigned special = dfp.a.bits & DECSPECIAL; \
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\
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if (shift_left) { \
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decNumberFromUInt32(&shd, sh); \
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} else { \
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decNumberFromInt32(&shd, -((int32_t)sh)); \
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} \
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\
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dfp.a.bits &= ~DECSPECIAL; \
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decNumberShift(&dfp.t, &dfp.a, &shd, &dfp.context); \
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\
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dfp.t.bits |= special; \
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if (special && (dfp.t.digits >= max_digits)) { \
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dfp.t.digits = max_digits - 1; \
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} \
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\
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decimal##size##FromNumber((decimal##size *)dfp.t64, &dfp.t, \
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&dfp.context); \
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} else { \
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if ((size) == 64) { \
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dfp.t64[0] = dfp.a64[0] & 0xFFFC000000000000ULL; \
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dfp_clear_lmd_from_g5msb(dfp.t64); \
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} else { \
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dfp.t64[HI_IDX] = dfp.a64[HI_IDX] & \
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0xFFFFC00000000000ULL; \
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dfp_clear_lmd_from_g5msb(dfp.t64 + HI_IDX); \
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dfp.t64[LO_IDX] = 0; \
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} \
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} \
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\
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if ((size) == 64) { \
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t[0] = dfp.t64[0]; \
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} else { \
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t[0] = dfp.t64[HI_IDX]; \
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t[1] = dfp.t64[LO_IDX]; \
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} \
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}
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DFP_HELPER_SHIFT(dscli, 64, 1)
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DFP_HELPER_SHIFT(dscliq, 128, 1)
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DFP_HELPER_SHIFT(dscri, 64, 0)
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DFP_HELPER_SHIFT(dscriq, 128, 0)
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@ -662,3 +662,7 @@ DEF_HELPER_3(dxex, void, env, fprp, fprp)
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DEF_HELPER_3(dxexq, void, env, fprp, fprp)
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DEF_HELPER_3(dxexq, void, env, fprp, fprp)
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DEF_HELPER_4(diex, void, env, fprp, fprp, fprp)
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DEF_HELPER_4(diex, void, env, fprp, fprp, fprp)
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DEF_HELPER_4(diexq, void, env, fprp, fprp, fprp)
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DEF_HELPER_4(diexq, void, env, fprp, fprp, fprp)
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DEF_HELPER_4(dscri, void, env, fprp, fprp, i32)
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DEF_HELPER_4(dscriq, void, env, fprp, fprp, i32)
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DEF_HELPER_4(dscli, void, env, fprp, fprp, i32)
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DEF_HELPER_4(dscliq, void, env, fprp, fprp, i32)
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@ -8402,6 +8402,11 @@ GEN_DFP_T_B_Rc(dxex)
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GEN_DFP_T_B_Rc(dxexq)
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GEN_DFP_T_B_Rc(dxexq)
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GEN_DFP_T_A_B_Rc(diex)
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GEN_DFP_T_A_B_Rc(diex)
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GEN_DFP_T_A_B_Rc(diexq)
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GEN_DFP_T_A_B_Rc(diexq)
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GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
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GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
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GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
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GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
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/*** SPE extension ***/
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/*** SPE extension ***/
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/* Register moves */
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/* Register moves */
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@ -11375,6 +11380,11 @@ GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
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GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
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GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
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GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
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GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
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GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
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GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
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GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
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GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
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GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
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GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
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#undef GEN_SPE
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#undef GEN_SPE
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#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
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#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
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GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
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GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
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