usb/hcd-xhci: QOM parent field cleanup
Replace direct uses of XHCIState::pci_dev with QOM casts and rename it to parent_obj. Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber
parent
37034575d2
commit
9b7d3334d0
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@ -443,7 +443,10 @@ typedef struct XHCIInterrupter {
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} XHCIInterrupter;
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struct XHCIState {
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PCIDevice pci_dev;
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/*< private >*/
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PCIDevice parent_obj;
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/*< public >*/
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USBBus bus;
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qemu_irq irq;
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MemoryRegion mem;
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@ -659,7 +662,7 @@ static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
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assert((len % sizeof(uint32_t)) == 0);
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pci_dma_read(&xhci->pci_dev, addr, buf, len);
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pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
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for (i = 0; i < (len / sizeof(uint32_t)); i++) {
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buf[i] = le32_to_cpu(buf[i]);
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@ -677,7 +680,7 @@ static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
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for (i = 0; i < (len / sizeof(uint32_t)); i++) {
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tmp[i] = cpu_to_le32(buf[i]);
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}
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pci_dma_write(&xhci->pci_dev, addr, tmp, len);
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pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
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}
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static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
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@ -704,10 +707,11 @@ static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
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static void xhci_intx_update(XHCIState *xhci)
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{
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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int level = 0;
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if (msix_enabled(&xhci->pci_dev) ||
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msi_enabled(&xhci->pci_dev)) {
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if (msix_enabled(pci_dev) ||
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msi_enabled(pci_dev)) {
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return;
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}
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@ -723,9 +727,10 @@ static void xhci_intx_update(XHCIState *xhci)
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static void xhci_msix_update(XHCIState *xhci, int v)
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{
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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bool enabled;
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if (!msix_enabled(&xhci->pci_dev)) {
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if (!msix_enabled(pci_dev)) {
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return;
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}
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@ -736,17 +741,19 @@ static void xhci_msix_update(XHCIState *xhci, int v)
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if (enabled) {
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trace_usb_xhci_irq_msix_use(v);
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msix_vector_use(&xhci->pci_dev, v);
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msix_vector_use(pci_dev, v);
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xhci->intr[v].msix_used = true;
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} else {
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trace_usb_xhci_irq_msix_unuse(v);
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msix_vector_unuse(&xhci->pci_dev, v);
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msix_vector_unuse(pci_dev, v);
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xhci->intr[v].msix_used = false;
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}
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}
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static void xhci_intr_raise(XHCIState *xhci, int v)
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{
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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xhci->intr[v].erdp_low |= ERDP_EHB;
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xhci->intr[v].iman |= IMAN_IP;
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xhci->usbsts |= USBSTS_EINT;
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@ -759,15 +766,15 @@ static void xhci_intr_raise(XHCIState *xhci, int v)
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return;
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}
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if (msix_enabled(&xhci->pci_dev)) {
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if (msix_enabled(pci_dev)) {
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trace_usb_xhci_irq_msix(v);
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msix_notify(&xhci->pci_dev, v);
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msix_notify(pci_dev, v);
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return;
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}
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if (msi_enabled(&xhci->pci_dev)) {
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if (msi_enabled(pci_dev)) {
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trace_usb_xhci_irq_msi(v);
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msi_notify(&xhci->pci_dev, v);
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msi_notify(pci_dev, v);
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return;
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}
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@ -790,6 +797,7 @@ static void xhci_die(XHCIState *xhci)
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static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
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{
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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XHCIInterrupter *intr = &xhci->intr[v];
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XHCITRB ev_trb;
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dma_addr_t addr;
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@ -808,7 +816,7 @@ static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
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ev_trb.status, ev_trb.control);
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addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
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pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE);
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pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
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intr->er_ep_idx++;
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if (intr->er_ep_idx >= intr->er_size) {
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@ -955,9 +963,11 @@ static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
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static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
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dma_addr_t *addr)
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{
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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while (1) {
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TRBType type;
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pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE);
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pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
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trb->addr = ring->dequeue;
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trb->ccs = ring->ccs;
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le64_to_cpus(&trb->parameter);
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@ -990,6 +1000,7 @@ static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
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static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
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{
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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XHCITRB trb;
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int length = 0;
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dma_addr_t dequeue = ring->dequeue;
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@ -999,7 +1010,7 @@ static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
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while (1) {
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TRBType type;
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pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE);
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pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
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le64_to_cpus(&trb.parameter);
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le32_to_cpus(&trb.status);
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le32_to_cpus(&trb.control);
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@ -1051,7 +1062,7 @@ static void xhci_er_reset(XHCIState *xhci, int v)
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return;
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}
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dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
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pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg));
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pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
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le32_to_cpus(&seg.addr_low);
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le32_to_cpus(&seg.addr_high);
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le32_to_cpus(&seg.size);
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@ -1526,7 +1537,7 @@ static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
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int i;
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xfer->int_req = false;
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pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count);
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pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
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for (i = 0; i < xfer->trb_count; i++) {
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XHCITRB *trb = &xfer->trbs[i];
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dma_addr_t addr;
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@ -2111,7 +2122,7 @@ static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
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assert(slotid >= 1 && slotid <= xhci->numslots);
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dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
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poctx = ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid);
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poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
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ictx = xhci_mask64(pictx);
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octx = xhci_mask64(poctx);
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@ -2432,7 +2443,7 @@ static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
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/* TODO: actually implement real values here */
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bw_ctx[0] = 0;
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memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
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pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
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pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
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return CC_SUCCESS;
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}
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@ -2455,11 +2466,12 @@ static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
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static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
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{
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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uint32_t buf[8];
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uint32_t obuf[8];
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dma_addr_t paddr = xhci_mask64(addr);
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pci_dma_read(&xhci->pci_dev, paddr, &buf, 32);
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pci_dma_read(pci_dev, paddr, &buf, 32);
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memcpy(obuf, buf, sizeof(obuf));
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@ -2475,7 +2487,7 @@ static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
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obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
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}
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pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32);
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pci_dma_write(pci_dev, paddr, &obuf, 32);
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}
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static void xhci_process_commands(XHCIState *xhci)
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@ -3322,10 +3334,10 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
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XHCIState *xhci = XHCI(dev);
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xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */
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xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
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xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
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xhci->pci_dev.config[0x60] = 0x30; /* release number */
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dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
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dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
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dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
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dev->config[0x60] = 0x30; /* release number */
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usb_xhci_init(xhci);
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@ -3347,7 +3359,7 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
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xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci);
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xhci->irq = xhci->pci_dev.irq[0];
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xhci->irq = dev->irq[0];
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memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
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memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
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@ -3373,18 +3385,18 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
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memory_region_add_subregion(&xhci->mem, offset, &port->mem);
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}
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pci_register_bar(&xhci->pci_dev, 0,
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pci_register_bar(dev, 0,
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PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
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&xhci->mem);
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ret = pcie_endpoint_cap_init(&xhci->pci_dev, 0xa0);
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ret = pcie_endpoint_cap_init(dev, 0xa0);
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assert(ret >= 0);
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if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) {
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msi_init(&xhci->pci_dev, 0x70, xhci->numintrs, true, false);
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msi_init(dev, 0x70, xhci->numintrs, true, false);
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}
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if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) {
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msix_init(&xhci->pci_dev, xhci->numintrs,
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msix_init(dev, xhci->numintrs,
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&xhci->mem, 0, OFF_MSIX_TABLE,
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&xhci->mem, 0, OFF_MSIX_PBA,
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0x90);
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@ -3396,6 +3408,7 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
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static int usb_xhci_post_load(void *opaque, int version_id)
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{
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XHCIState *xhci = opaque;
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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XHCISlot *slot;
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XHCIEPContext *epctx;
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dma_addr_t dcbaap, pctx;
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@ -3411,7 +3424,7 @@ static int usb_xhci_post_load(void *opaque, int version_id)
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continue;
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}
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slot->ctx =
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xhci_mask64(ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid));
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xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
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xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
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slot->uport = xhci_lookup_uport(xhci, slot_ctx);
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assert(slot->uport && slot->uport->dev);
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@ -3436,9 +3449,9 @@ static int usb_xhci_post_load(void *opaque, int version_id)
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for (intr = 0; intr < xhci->numintrs; intr++) {
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if (xhci->intr[intr].msix_used) {
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msix_vector_use(&xhci->pci_dev, intr);
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msix_vector_use(pci_dev, intr);
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} else {
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msix_vector_unuse(&xhci->pci_dev, intr);
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msix_vector_unuse(pci_dev, intr);
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}
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}
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@ -3531,8 +3544,8 @@ static const VMStateDescription vmstate_xhci = {
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.version_id = 1,
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.post_load = usb_xhci_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCIE_DEVICE(pci_dev, XHCIState),
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VMSTATE_MSIX(pci_dev, XHCIState),
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VMSTATE_PCIE_DEVICE(parent_obj, XHCIState),
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VMSTATE_MSIX(parent_obj, XHCIState),
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VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
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vmstate_xhci_port, XHCIPort),
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