Change handling of source 2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4135 c046a42c-6fe2-441c-8c8c-71466251a162
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			@ -1834,6 +1834,26 @@ static inline TCGv get_src1(unsigned int insn, TCGv def)
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    return r_rs1;
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}
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static inline TCGv get_src2(unsigned int insn, TCGv def)
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{
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    TCGv r_rs2 = def;
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    unsigned int rs2;
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    if (IS_IMM) { /* immediate */
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        rs2 = GET_FIELDs(insn, 19, 31);
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        r_rs2 = tcg_const_tl((int)rs2);
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    } else { /* register */
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        rs2 = GET_FIELD(insn, 27, 31);
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        if (rs2 == 0)
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            r_rs2 = tcg_const_tl(0);
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        else if (rs2 < 8)
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            r_rs2 = cpu_gregs[rs2];
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        else
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            tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
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    }
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    return r_rs2;
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}
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/* before an instruction, dc->pc must be static */
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static void disas_sparc_insn(DisasContext * dc)
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{
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			@ -2949,13 +2969,7 @@ static void disas_sparc_insn(DisasContext * dc)
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#endif
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            } else if (xop < 0x36) {
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                cpu_src1 = get_src1(insn, cpu_src1);
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                if (IS_IMM) {   /* immediate */
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                    rs2 = GET_FIELDs(insn, 19, 31);
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                    tcg_gen_movi_tl(cpu_src2, (int)rs2);
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                } else {                /* register */
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                    rs2 = GET_FIELD(insn, 27, 31);
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                    gen_movl_reg_TN(rs2, cpu_src2);
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                }
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                cpu_src2 = get_src2(insn, cpu_src2);
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                if (xop < 0x20) {
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                    switch (xop & ~0x10) {
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                    case 0x0:
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			@ -3469,15 +3483,7 @@ static void disas_sparc_insn(DisasContext * dc)
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                        break;
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                    case 0x2e: /* V9 popc */
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                        {
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                            if (IS_IMM) {       /* immediate */
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                                rs2 = GET_FIELD_SPs(insn, 0, 12);
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                                tcg_gen_movi_tl(cpu_src2, (int)rs2);
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                                // XXX optimize: popc(constant)
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                            }
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                            else {
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                                rs2 = GET_FIELD_SP(insn, 0, 4);
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                                gen_movl_reg_TN(rs2, cpu_src2);
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                            }
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                            cpu_src2 = get_src2(insn, cpu_src2);
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                            tcg_gen_helper_1_1(helper_popc, cpu_dst,
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                                               cpu_src2);
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                            gen_movl_TN_reg(rd, cpu_dst);
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