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Fix APB 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6265 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2009-01-09 20:53:30 +00:00
parent 27a3deca51
commit a94fd955eb
2 changed files with 28 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
hw/apb_pci.c
View File

@ -22,12 +22,23 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
/* XXX This file and most of its contests are somewhat misnamed. The /* XXX This file and most of its contents are somewhat misnamed. The
Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
the secondary PCI bridge. */ the secondary PCI bridge. */
#include "hw.h" #include "hw.h"
#include "pci.h" #include "pci.h"
/* debug APB */
//#define DEBUG_APB
#ifdef DEBUG_APB
#define APB_DPRINTF(fmt, args...) \
do { printf("APB: " fmt , ##args); } while (0)
#else
#define APB_DPRINTF(fmt, args...)
#endif
typedef target_phys_addr_t pci_addr_t; typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h" #include "pci_host.h"
@ -37,13 +48,13 @@ static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val) uint32_t val)
{ {
APBState *s = opaque; APBState *s = opaque;
int i;
for (i = 11; i < 32; i++) { #ifdef TARGET_WORDS_BIGENDIAN
if ((val & (1 << i)) != 0) val = bswap32(val);
break; #endif
} APB_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
s->config_reg = (1 << 16) | (val & 0x7FC) | (i << 11); val);
s->config_reg = val;
} }
static uint32_t pci_apb_config_readl (void *opaque, static uint32_t pci_apb_config_readl (void *opaque,
@ -51,10 +62,13 @@ static uint32_t pci_apb_config_readl (void *opaque,
{ {
APBState *s = opaque; APBState *s = opaque;
uint32_t val; uint32_t val;
int devfn;
devfn = (s->config_reg >> 8) & 0xFF; val = s->config_reg;
val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC); #ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
APB_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
val);
return val; return val;
} }
@ -259,5 +273,5 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
"Advanced PCI Bus secondary bridge 1"); "Advanced PCI Bus secondary bridge 1");
pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq, pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq,
"Advanced PCI Bus secondary bridge 2"); "Advanced PCI Bus secondary bridge 2");
return secondary; return s->bus;
} }

5
hw/sun4u.c
View File

@ -465,8 +465,9 @@ static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL); pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
isa_mem_base = VGA_BASE; isa_mem_base = VGA_BASE;
vga_ram_offset = qemu_ram_alloc(vga_ram_size); vga_ram_offset = qemu_ram_alloc(vga_ram_size);
pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset, pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset,
vga_ram_offset, vga_ram_size); vga_ram_offset, vga_ram_size,
0, 0);
i = 0; i = 0;
if (hwdef->console_serial_base) { if (hwdef->console_serial_base) {