hw/ide: Emulate SiI3112 SATA controller
This is a common generic PCI SATA controller that is also used in PCs but more importantly guests running on the Sam460ex board prefer this card and have a driver for it (unlike for other SATA controllers already emulated). Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: John Snow <jsnow@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
BALATON Zoltan
David Gibson
parent
2b3db9dd34
commit
a9dd6604a6
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@ -765,6 +765,12 @@ L: qemu-ppc@nongnu.org
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S: Odd Fixes
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F: hw/ppc/virtex_ml507.c
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sam460ex
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M: BALATON Zoltan <balaton@eik.bme.hu>
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L: qemu-ppc@nongnu.org
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S: Maintained
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F: hw/ide/sii3112.c
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SH4 Machines
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------------
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R2D
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@ -16,3 +16,4 @@ CONFIG_I8259=y
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CONFIG_XILINX=y
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CONFIG_XILINX_ETHLITE=y
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CONFIG_SM501=y
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CONFIG_IDE_SII3112=y
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@ -11,3 +11,4 @@ common-obj-$(CONFIG_MICRODRIVE) += microdrive.o
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common-obj-$(CONFIG_AHCI) += ahci.o
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common-obj-$(CONFIG_AHCI) += ich.o
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common-obj-$(CONFIG_ALLWINNER_A10) += ahci-allwinner.o
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common-obj-$(CONFIG_IDE_SII3112) += sii3112.o
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@ -0,0 +1,368 @@
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/*
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* QEMU SiI3112A PCI to Serial ATA Controller Emulation
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*
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* Copyright (C) 2017 BALATON Zoltan <balaton@eik.bme.hu>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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/* For documentation on this and similar cards see:
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* http://wiki.osdev.org/User:Quok/Silicon_Image_Datasheets
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*/
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#include <qemu/osdep.h>
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#include <hw/ide/pci.h>
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#include "trace.h"
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#define TYPE_SII3112_PCI "sii3112"
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#define SII3112_PCI(obj) OBJECT_CHECK(SiI3112PCIState, (obj), \
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TYPE_SII3112_PCI)
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typedef struct SiI3112Regs {
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uint32_t confstat;
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uint32_t scontrol;
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uint16_t sien;
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uint8_t swdata;
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} SiI3112Regs;
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typedef struct SiI3112PCIState {
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PCIIDEState i;
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MemoryRegion mmio;
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SiI3112Regs regs[2];
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} SiI3112PCIState;
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/* The sii3112_reg_read and sii3112_reg_write functions implement the
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* Internal Register Space - BAR5 (section 6.7 of the data sheet).
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*/
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static uint64_t sii3112_reg_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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SiI3112PCIState *d = opaque;
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uint64_t val = 0;
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switch (addr) {
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case 0x00:
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val = d->i.bmdma[0].cmd;
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break;
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case 0x01:
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val = d->regs[0].swdata;
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break;
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case 0x02:
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val = d->i.bmdma[0].status;
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break;
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case 0x03:
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val = 0;
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break;
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case 0x04 ... 0x07:
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val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size);
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break;
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case 0x08:
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val = d->i.bmdma[1].cmd;
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break;
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case 0x09:
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val = d->regs[1].swdata;
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break;
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case 0x0a:
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val = d->i.bmdma[1].status;
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break;
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case 0x0b:
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val = 0;
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break;
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case 0x0c ... 0x0f:
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val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size);
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break;
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case 0x10:
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val = d->i.bmdma[0].cmd;
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val |= (d->regs[0].confstat & (1UL << 11) ? (1 << 4) : 0); /*SATAINT0*/
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val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 6) : 0); /*SATAINT1*/
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val |= (d->i.bmdma[1].status & BM_STATUS_INT ? (1 << 14) : 0);
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val |= d->i.bmdma[0].status << 16;
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val |= d->i.bmdma[1].status << 24;
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break;
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case 0x18:
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val = d->i.bmdma[1].cmd;
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val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 4) : 0);
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val |= d->i.bmdma[1].status << 16;
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break;
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case 0x80 ... 0x87:
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if (size == 1) {
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val = ide_ioport_read(&d->i.bus[0], addr - 0x80);
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} else if (addr == 0x80) {
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val = (size == 2) ? ide_data_readw(&d->i.bus[0], 0) :
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ide_data_readl(&d->i.bus[0], 0);
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} else {
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val = (1ULL << (size * 8)) - 1;
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}
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break;
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case 0x8a:
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val = (size == 1) ? ide_status_read(&d->i.bus[0], 4) :
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(1ULL << (size * 8)) - 1;
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break;
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case 0xa0:
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val = d->regs[0].confstat;
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break;
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case 0xc0 ... 0xc7:
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if (size == 1) {
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val = ide_ioport_read(&d->i.bus[1], addr - 0xc0);
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} else if (addr == 0xc0) {
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val = (size == 2) ? ide_data_readw(&d->i.bus[1], 0) :
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ide_data_readl(&d->i.bus[1], 0);
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} else {
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val = (1ULL << (size * 8)) - 1;
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}
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break;
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case 0xca:
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val = (size == 1) ? ide_status_read(&d->i.bus[0], 4) :
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(1ULL << (size * 8)) - 1;
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break;
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case 0xe0:
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val = d->regs[1].confstat;
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break;
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case 0x100:
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val = d->regs[0].scontrol;
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break;
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case 0x104:
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val = (d->i.bus[0].ifs[0].blk) ? 0x113 : 0;
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break;
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case 0x148:
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val = d->regs[0].sien << 16;
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break;
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case 0x180:
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val = d->regs[1].scontrol;
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break;
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case 0x184:
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val = (d->i.bus[1].ifs[0].blk) ? 0x113 : 0;
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break;
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case 0x1c8:
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val = d->regs[1].sien << 16;
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break;
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default:
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val = 0;
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}
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trace_sii3112_read(size, addr, val);
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return val;
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}
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static void sii3112_reg_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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SiI3112PCIState *d = opaque;
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trace_sii3112_write(size, addr, val);
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switch (addr) {
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case 0x00:
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case 0x10:
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bmdma_cmd_writeb(&d->i.bmdma[0], val);
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break;
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case 0x01:
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case 0x11:
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d->regs[0].swdata = val & 0x3f;
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break;
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case 0x02:
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case 0x12:
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d->i.bmdma[0].status = (val & 0x60) | (d->i.bmdma[0].status & 1) |
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(d->i.bmdma[0].status & ~val & 6);
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break;
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case 0x04 ... 0x07:
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bmdma_addr_ioport_ops.write(&d->i.bmdma[0], addr - 4, val, size);
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break;
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case 0x08:
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case 0x18:
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bmdma_cmd_writeb(&d->i.bmdma[1], val);
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break;
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case 0x09:
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case 0x19:
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d->regs[1].swdata = val & 0x3f;
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break;
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case 0x0a:
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case 0x1a:
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d->i.bmdma[1].status = (val & 0x60) | (d->i.bmdma[1].status & 1) |
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(d->i.bmdma[1].status & ~val & 6);
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break;
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case 0x0c ... 0x0f:
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bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size);
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break;
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case 0x80 ... 0x87:
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if (size == 1) {
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ide_ioport_write(&d->i.bus[0], addr - 0x80, val);
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} else if (addr == 0x80) {
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if (size == 2) {
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ide_data_writew(&d->i.bus[0], 0, val);
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} else {
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ide_data_writel(&d->i.bus[0], 0, val);
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}
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}
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break;
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case 0x8a:
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if (size == 1) {
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ide_cmd_write(&d->i.bus[0], 4, val);
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}
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break;
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case 0xc0 ... 0xc7:
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if (size == 1) {
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ide_ioport_write(&d->i.bus[1], addr - 0xc0, val);
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} else if (addr == 0xc0) {
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if (size == 2) {
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ide_data_writew(&d->i.bus[1], 0, val);
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} else {
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ide_data_writel(&d->i.bus[1], 0, val);
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}
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}
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break;
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case 0xca:
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if (size == 1) {
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ide_cmd_write(&d->i.bus[1], 4, val);
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}
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break;
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case 0x100:
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d->regs[0].scontrol = val & 0xfff;
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if (val & 1) {
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ide_bus_reset(&d->i.bus[0]);
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}
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break;
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case 0x148:
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d->regs[0].sien = (val >> 16) & 0x3eed;
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break;
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case 0x180:
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d->regs[1].scontrol = val & 0xfff;
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if (val & 1) {
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ide_bus_reset(&d->i.bus[1]);
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}
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break;
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case 0x1c8:
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d->regs[1].sien = (val >> 16) & 0x3eed;
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break;
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default:
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val = 0;
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}
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}
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static const MemoryRegionOps sii3112_reg_ops = {
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.read = sii3112_reg_read,
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.write = sii3112_reg_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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/* the PCI irq level is the logical OR of the two channels */
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static void sii3112_update_irq(SiI3112PCIState *s)
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{
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int i, set = 0;
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for (i = 0; i < 2; i++) {
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set |= s->regs[i].confstat & (1UL << 11);
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}
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pci_set_irq(PCI_DEVICE(s), (set ? 1 : 0));
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}
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static void sii3112_set_irq(void *opaque, int channel, int level)
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{
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SiI3112PCIState *s = opaque;
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trace_sii3112_set_irq(channel, level);
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if (level) {
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s->regs[channel].confstat |= (1UL << 11);
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} else {
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s->regs[channel].confstat &= ~(1UL << 11);
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}
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sii3112_update_irq(s);
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}
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static void sii3112_reset(void *opaque)
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{
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SiI3112PCIState *s = opaque;
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int i;
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for (i = 0; i < 2; i++) {
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s->regs[i].confstat = 0x6515 << 16;
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ide_bus_reset(&s->i.bus[i]);
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}
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}
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static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
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{
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SiI3112PCIState *d = SII3112_PCI(dev);
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PCIIDEState *s = PCI_IDE(dev);
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MemoryRegion *mr;
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qemu_irq *irq;
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int i;
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pci_config_set_interrupt_pin(dev->config, 1);
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pci_set_byte(dev->config + PCI_CACHE_LINE_SIZE, 8);
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/* BAR5 is in PCI memory space */
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memory_region_init_io(&d->mmio, OBJECT(d), &sii3112_reg_ops, d,
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"sii3112.bar5", 0x200);
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pci_register_bar(dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
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/* BAR0-BAR4 are PCI I/O space aliases into BAR5 */
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mr = g_new(MemoryRegion, 1);
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memory_region_init_alias(mr, OBJECT(d), "sii3112.bar0", &d->mmio, 0x80, 8);
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pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, mr);
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mr = g_new(MemoryRegion, 1);
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memory_region_init_alias(mr, OBJECT(d), "sii3112.bar1", &d->mmio, 0x88, 4);
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pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, mr);
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mr = g_new(MemoryRegion, 1);
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memory_region_init_alias(mr, OBJECT(d), "sii3112.bar2", &d->mmio, 0xc0, 8);
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pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, mr);
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mr = g_new(MemoryRegion, 1);
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memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &d->mmio, 0xc8, 4);
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pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, mr);
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mr = g_new(MemoryRegion, 1);
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memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &d->mmio, 0, 16);
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pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, mr);
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irq = qemu_allocate_irqs(sii3112_set_irq, d, 2);
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for (i = 0; i < 2; i++) {
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ide_bus_new(&s->bus[i], sizeof(s->bus[i]), DEVICE(dev), i, 1);
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ide_init2(&s->bus[i], irq[i]);
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bmdma_init(&s->bus[i], &s->bmdma[i], s);
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s->bmdma[i].bus = &s->bus[i];
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ide_register_restart_cb(&s->bus[i]);
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}
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qemu_register_reset(sii3112_reset, s);
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}
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static void sii3112_pci_exitfn(PCIDevice *dev)
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{
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PCIIDEState *d = PCI_IDE(dev);
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int i;
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for (i = 0; i < 2; ++i) {
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
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}
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}
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static void sii3112_pci_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *pd = PCI_DEVICE_CLASS(klass);
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pd->vendor_id = 0x1095;
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pd->device_id = 0x3112;
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pd->class_id = PCI_CLASS_STORAGE_RAID;
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pd->revision = 1;
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pd->realize = sii3112_pci_realize;
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pd->exit = sii3112_pci_exitfn;
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dc->desc = "SiI3112A SATA controller";
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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}
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static const TypeInfo sii3112_pci_info = {
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.name = TYPE_SII3112_PCI,
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.parent = TYPE_PCI_IDE,
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.instance_size = sizeof(SiI3112PCIState),
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.class_init = sii3112_pci_class_init,
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};
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static void sii3112_register_types(void)
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{
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type_register_static(&sii3112_pci_info);
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}
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type_init(sii3112_register_types)
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@ -37,6 +37,11 @@ bmdma_addr_write(uint64_t data) "data: 0x%016"PRIx64
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bmdma_read(uint64_t addr, uint8_t val) "bmdma: readb 0x%"PRIx64" : 0x%02x"
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bmdma_write(uint64_t addr, uint64_t val) "bmdma: writeb 0x%"PRIx64" : 0x%02"PRIx64
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# hw/ide/sii3112.c
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sii3112_read(int size, uint64_t addr, uint64_t val) "bmdma: read (size %d) 0x%"PRIx64" : 0x%02"PRIx64
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sii3112_write(int size, uint64_t addr, uint64_t val) "bmdma: write (size %d) 0x%"PRIx64" : 0x%02"PRIx64
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sii3112_set_irq(int channel, int level) "channel %d level %d"
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# hw/ide/via.c
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bmdma_read_via(uint64_t addr, uint32_t val) "bmdma: readb 0x%"PRIx64" : 0x%02x"
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bmdma_write_via(uint64_t addr, uint64_t val) "bmdma: writeb 0x%"PRIx64" : 0x%02"PRIx64
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