target-xtensa: fix build for cores w/o windowed registers
Cores without windowed registers don't have window overflow/underflow vectors. Move these vectors to a separate group defined conditionally. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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			@ -108,8 +108,8 @@
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#define XCHAL_WINDOW_UF12_VECOFS        0x00000140
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#endif
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#define EXCEPTION_VECTORS { \
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        [EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
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#if XCHAL_HAVE_WINDOWED
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#define WINDOW_VECTORS \
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   [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
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       XCHAL_WINDOW_VECTORS_VADDR, \
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   [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
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			@ -121,7 +121,14 @@
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   [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
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       XCHAL_WINDOW_VECTORS_VADDR, \
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   [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
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            XCHAL_WINDOW_VECTORS_VADDR, \
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       XCHAL_WINDOW_VECTORS_VADDR,
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#else
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#define WINDOW_VECTORS
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#endif
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#define EXCEPTION_VECTORS { \
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        [EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
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        WINDOW_VECTORS \
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        [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
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        [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
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        [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
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