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target-ppc: convert fp ops to TCG 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5754 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-11-19 16:10:23 +00:00
parent a3d6841ff8
commit af12906f77
6 changed files with 550 additions and 636 deletions
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1
target-ppc/cpu.h
View File

@ -571,7 +571,6 @@ struct CPUPPCState {
/* temporary float registers */
float64 ft0;
float64 ft1;
float64 ft2;
float_status fp_status;
/* floating point registers */
float64 fpr[32];

1
target-ppc/exec.h
View File

@ -61,7 +61,6 @@ register target_ulong T2 asm(AREG3);
#define FT0 (env->ft0)
#define FT1 (env->ft1)
#define FT2 (env->ft2)
#if defined (DEBUG_OP)
# define RETURN() __asm__ __volatile__("nop" : : : "memory");

42
target-ppc/helper.h
View File

@ -1,7 +1,7 @@
#include "def-helper.h"
DEF_HELPER_0(fcmpo, i32)
DEF_HELPER_0(fcmpu, i32)
DEF_HELPER_2(fcmpo, i32, i64, i64)
DEF_HELPER_2(fcmpu, i32, i64, i64)
DEF_HELPER_0(load_cr, tl)
DEF_HELPER_2(store_cr, void, tl, i32)
@ -25,4 +25,42 @@ DEF_HELPER_1(cntlsw32, i32, i32)
DEF_HELPER_1(cntlzw32, i32, i32)
DEF_HELPER_2(brinc, tl, tl, tl)
DEF_HELPER_0(float_check_status, void)
#ifdef CONFIG_SOFTFLOAT
DEF_HELPER_0(reset_fpstatus, void)
#endif
DEF_HELPER_2(compute_fprf, i32, i64, i32)
DEF_HELPER_2(store_fpscr, void, i64, i32)
DEF_HELPER_1(fpscr_setbit, void, i32)
DEF_HELPER_1(fctiw, i64, i64)
DEF_HELPER_1(fctiwz, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_1(fcfid, i64, i64)
DEF_HELPER_1(fctid, i64, i64)
DEF_HELPER_1(fctidz, i64, i64)
#endif
DEF_HELPER_1(frsp, i64, i64)
DEF_HELPER_1(frin, i64, i64)
DEF_HELPER_1(friz, i64, i64)
DEF_HELPER_1(frip, i64, i64)
DEF_HELPER_1(frim, i64, i64)
DEF_HELPER_2(fadd, i64, i64, i64)
DEF_HELPER_2(fsub, i64, i64, i64)
DEF_HELPER_2(fmul, i64, i64, i64)
DEF_HELPER_2(fdiv, i64, i64, i64)
DEF_HELPER_3(fmadd, i64, i64, i64, i64)
DEF_HELPER_3(fmsub, i64, i64, i64, i64)
DEF_HELPER_3(fnmadd, i64, i64, i64, i64)
DEF_HELPER_3(fnmsub, i64, i64, i64, i64)
DEF_HELPER_1(fabs, i64, i64)
DEF_HELPER_1(fnabs, i64, i64)
DEF_HELPER_1(fneg, i64, i64)
DEF_HELPER_1(fsqrt, i64, i64);
DEF_HELPER_1(fre, i64, i64);
DEF_HELPER_1(fres, i64, i64);
DEF_HELPER_1(frsqrte, i64, i64);
DEF_HELPER_3(fsel, i64, i64, i64, i64)
#include "def-helper.h"

280
target-ppc/op.c
View File

@ -261,71 +261,6 @@ void OPPROTO op_store_dbatl (void)
}
#endif /* !defined(CONFIG_USER_ONLY) */
/* FPSCR */
#ifdef CONFIG_SOFTFLOAT
void OPPROTO op_reset_fpstatus (void)
{
env->fp_status.float_exception_flags = 0;
RETURN();
}
#endif
void OPPROTO op_compute_fprf (void)
{
do_compute_fprf(PARAM1);
RETURN();
}
#ifdef CONFIG_SOFTFLOAT
void OPPROTO op_float_check_status (void)
{
do_float_check_status();
RETURN();
}
#else
void OPPROTO op_float_check_status (void)
{
if (env->exception_index == POWERPC_EXCP_PROGRAM &&
(env->error_code & POWERPC_EXCP_FP)) {
/* Differred floating-point exception after target FPR update */
if (msr_fe0 != 0 || msr_fe1 != 0)
do_raise_exception_err(env->exception_index, env->error_code);
}
RETURN();
}
#endif
void OPPROTO op_load_fpscr_FT0 (void)
{
/* The 32 MSB of the target fpr are undefined.
* They'll be zero...
*/
CPU_DoubleU u;
u.l.upper = 0;
u.l.lower = env->fpscr;
FT0 = u.d;
RETURN();
}
void OPPROTO op_fpscr_resetbit (void)
{
env->fpscr &= PARAM1;
RETURN();
}
void OPPROTO op_fpscr_setbit (void)
{
do_fpscr_setbit(PARAM1);
RETURN();
}
void OPPROTO op_store_fpscr (void)
{
do_store_fpscr(PARAM1);
RETURN();
}
/*** Integer shift ***/
void OPPROTO op_srli_T1 (void)
{
@ -333,221 +268,6 @@ void OPPROTO op_srli_T1 (void)
RETURN();
}
/*** Floating-Point arithmetic ***/
/* fadd - fadd. */
void OPPROTO op_fadd (void)
{
#if USE_PRECISE_EMULATION
do_fadd();
#else
FT0 = float64_add(FT0, FT1, &env->fp_status);
#endif
RETURN();
}
/* fsub - fsub. */
void OPPROTO op_fsub (void)
{
#if USE_PRECISE_EMULATION
do_fsub();
#else
FT0 = float64_sub(FT0, FT1, &env->fp_status);
#endif
RETURN();
}
/* fmul - fmul. */
void OPPROTO op_fmul (void)
{
#if USE_PRECISE_EMULATION
do_fmul();
#else
FT0 = float64_mul(FT0, FT1, &env->fp_status);
#endif
RETURN();
}
/* fdiv - fdiv. */
void OPPROTO op_fdiv (void)
{
#if USE_PRECISE_EMULATION
do_fdiv();
#else
FT0 = float64_div(FT0, FT1, &env->fp_status);
#endif
RETURN();
}
/* fsqrt - fsqrt. */
void OPPROTO op_fsqrt (void)
{
do_fsqrt();
RETURN();
}
/* fre - fre. */
void OPPROTO op_fre (void)
{
do_fre();
RETURN();
}
/* fres - fres. */
void OPPROTO op_fres (void)
{
do_fres();
RETURN();
}
/* frsqrte - frsqrte. */
void OPPROTO op_frsqrte (void)
{
do_frsqrte();
RETURN();
}
/* fsel - fsel. */
void OPPROTO op_fsel (void)
{
do_fsel();
RETURN();
}
/*** Floating-Point multiply-and-add ***/
/* fmadd - fmadd. */
void OPPROTO op_fmadd (void)
{
#if USE_PRECISE_EMULATION
do_fmadd();
#else
FT0 = float64_mul(FT0, FT1, &env->fp_status);
FT0 = float64_add(FT0, FT2, &env->fp_status);
#endif
RETURN();
}
/* fmsub - fmsub. */
void OPPROTO op_fmsub (void)
{
#if USE_PRECISE_EMULATION
do_fmsub();
#else
FT0 = float64_mul(FT0, FT1, &env->fp_status);
FT0 = float64_sub(FT0, FT2, &env->fp_status);
#endif
RETURN();
}
/* fnmadd - fnmadd. - fnmadds - fnmadds. */
void OPPROTO op_fnmadd (void)
{
do_fnmadd();
RETURN();
}
/* fnmsub - fnmsub. */
void OPPROTO op_fnmsub (void)
{
do_fnmsub();
RETURN();
}
/*** Floating-Point round & convert ***/
/* frsp - frsp. */
void OPPROTO op_frsp (void)
{
#if USE_PRECISE_EMULATION
do_frsp();
#else
FT0 = float64_to_float32(FT0, &env->fp_status);
#endif
RETURN();
}
/* fctiw - fctiw. */
void OPPROTO op_fctiw (void)
{
do_fctiw();
RETURN();
}
/* fctiwz - fctiwz. */
void OPPROTO op_fctiwz (void)
{
do_fctiwz();
RETURN();
}
#if defined(TARGET_PPC64)
/* fcfid - fcfid. */
void OPPROTO op_fcfid (void)
{
do_fcfid();
RETURN();
}
/* fctid - fctid. */
void OPPROTO op_fctid (void)
{
do_fctid();
RETURN();
}
/* fctidz - fctidz. */
void OPPROTO op_fctidz (void)
{
do_fctidz();
RETURN();
}
#endif
void OPPROTO op_frin (void)
{
do_frin();
RETURN();
}
void OPPROTO op_friz (void)
{
do_friz();
RETURN();
}
void OPPROTO op_frip (void)
{
do_frip();
RETURN();
}
void OPPROTO op_frim (void)
{
do_frim();
RETURN();
}
/*** Floating-point move ***/
/* fabs */
void OPPROTO op_fabs (void)
{
FT0 = float64_abs(FT0);
RETURN();
}
/* fnabs */
void OPPROTO op_fnabs (void)
{
FT0 = float64_abs(FT0);
FT0 = float64_chs(FT0);
RETURN();
}
/* fneg */
void OPPROTO op_fneg (void)
{
FT0 = float64_chs(FT0);
RETURN();
}
/* Load and store */
#define MEMSUFFIX _raw
#include "op_helper.h"

705
target-ppc/op_helper.c
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File diff suppressed because it is too large Load Diff

157
target-ppc/translate.c
View File

@ -75,7 +75,7 @@ static TCGv cpu_T[3];
#else
static TCGv_i64 cpu_T64[3];
#endif
static TCGv_i64 cpu_FT[3];
static TCGv_i64 cpu_FT[2];
static TCGv_i64 cpu_AVRh[3], cpu_AVRl[3];
#include "gen-icount.h"
@ -120,8 +120,6 @@ void ppc_translate_init(void)
offsetof(CPUState, ft0), "FT0");
cpu_FT[1] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUState, ft1), "FT1");
cpu_FT[2] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUState, ft2), "FT2");
cpu_AVRh[0] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUState, avr0.u64[0]), "AVR0H");
@ -245,27 +243,31 @@ static always_inline void gen_reset_fpstatus (void)
#endif
}
static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
static always_inline void gen_compute_fprf (TCGv arg, int set_fprf, int set_rc)
{
TCGv t0 = tcg_temp_new_i32();
if (set_fprf != 0) {
/* This case might be optimized later */
#if defined(OPTIMIZE_FPRF_UPDATE)
*gen_fprf_ptr++ = gen_opc_ptr;
#endif
gen_op_compute_fprf(1);
tcg_gen_movi_tl(t0, 1);
gen_helper_compute_fprf(t0, arg, t0);
if (unlikely(set_rc)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_T[0]);
tcg_gen_andi_i32(cpu_crf[1], cpu_crf[1], 0xf);
tcg_gen_movi_i32(cpu_crf[1], t0);
}
gen_op_float_check_status();
gen_helper_float_check_status();
} else if (unlikely(set_rc)) {
/* We always need to compute fpcc */
gen_op_compute_fprf(0);
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_T[0]);
tcg_gen_andi_i32(cpu_crf[1], cpu_crf[1], 0xf);
tcg_gen_movi_tl(t0, 0);
gen_helper_compute_fprf(t0, arg, t0);
tcg_gen_movi_i32(cpu_crf[1], t0);
if (set_fprf)
gen_op_float_check_status();
gen_helper_float_check_status();
}
tcg_temp_free(t0);
}
static always_inline void gen_optimize_fprf (void)
@ -2096,16 +2098,14 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
GEN_EXCP_NO_FP(ctx); \
return; \
} \
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
gen_reset_fpstatus(); \
gen_op_f##op(); \
gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
if (isfloat) { \
gen_op_frsp(); \
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
} \
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
Rc(ctx->opcode) != 0); \
}
#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
@ -2119,15 +2119,14 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
GEN_EXCP_NO_FP(ctx); \
return; \
} \
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
gen_reset_fpstatus(); \
gen_op_f##op(); \
gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
cpu_fpr[rB(ctx->opcode)]); \
if (isfloat) { \
gen_op_frsp(); \
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
} \
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
set_fprf, Rc(ctx->opcode) != 0); \
}
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
@ -2140,15 +2139,14 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
GEN_EXCP_NO_FP(ctx); \
return; \
} \
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
gen_reset_fpstatus(); \
gen_op_f##op(); \
gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
cpu_fpr[rC(ctx->opcode)]); \
if (isfloat) { \
gen_op_frsp(); \
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
} \
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
set_fprf, Rc(ctx->opcode) != 0); \
}
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
@ -2161,11 +2159,10 @@ GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
GEN_EXCP_NO_FP(ctx); \
return; \
} \
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
gen_reset_fpstatus(); \
gen_op_f##name(); \
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
set_fprf, Rc(ctx->opcode) != 0); \
}
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
@ -2175,11 +2172,10 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
GEN_EXCP_NO_FP(ctx); \
return; \
} \
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
gen_reset_fpstatus(); \
gen_op_f##name(); \
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
set_fprf, Rc(ctx->opcode) != 0); \
}
/* fadd - fadds */
@ -2199,12 +2195,17 @@ GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
/* frsqrtes */
static always_inline void gen_op_frsqrtes (void)
GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
{
gen_op_frsqrte();
gen_op_frsp();
if (unlikely(!ctx->fpu_enabled)) {
GEN_EXCP_NO_FP(ctx);
return;
}
gen_reset_fpstatus();
gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
}
GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
/* fsel */
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
@ -2218,11 +2219,9 @@ GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
GEN_EXCP_NO_FP(ctx);
return;
}
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
gen_reset_fpstatus();
gen_op_fsqrt();
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
gen_compute_fprf(1, Rc(ctx->opcode) != 0);
gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
}
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
@ -2231,12 +2230,10 @@ GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
GEN_EXCP_NO_FP(ctx);
return;
}
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
gen_reset_fpstatus();
gen_op_fsqrt();
gen_op_frsp();
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
gen_compute_fprf(1, Rc(ctx->opcode) != 0);
gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
}
/*** Floating-Point multiply-and-add ***/
@ -2282,11 +2279,10 @@ GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
GEN_EXCP_NO_FP(ctx);
return;
}
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
gen_reset_fpstatus();
gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)]);
gen_op_float_check_status();
gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)],
cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
gen_helper_float_check_status();
}
/* fcmpu */
@ -2296,11 +2292,10 @@ GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
GEN_EXCP_NO_FP(ctx);
return;
}
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
gen_reset_fpstatus();
gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)]);
gen_op_float_check_status();
gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)],
cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
gen_helper_float_check_status();
}
/*** Floating-point move ***/
@ -2316,9 +2311,8 @@ GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
GEN_EXCP_NO_FP(ctx);
return;
}
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
gen_compute_fprf(0, Rc(ctx->opcode) != 0);
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
}
/* fnabs */
@ -2342,7 +2336,7 @@ GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
bfa = 4 * (7 - crfS(ctx->opcode));
tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
gen_op_fpscr_resetbit(~(0xF << bfa));
tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
}
/* mffs */
@ -2354,9 +2348,8 @@ GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
}
gen_optimize_fprf();
gen_reset_fpstatus();
gen_op_load_fpscr_FT0();
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
gen_compute_fprf(0, Rc(ctx->opcode) != 0);
tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
}
/* mtfsb0 */
@ -2372,7 +2365,7 @@ GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
gen_optimize_fprf();
gen_reset_fpstatus();
if (likely(crb != 30 && crb != 29))
gen_op_fpscr_resetbit(~(1 << crb));
tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
}
@ -2391,37 +2384,44 @@ GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
gen_optimize_fprf();
gen_reset_fpstatus();
/* XXX: we pretend we can only do IEEE floating-point computations */
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
gen_op_fpscr_setbit(crb);
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
TCGv t0 = tcg_const_tl(crb);
gen_helper_fpscr_setbit(t0);
tcg_temp_free(t0);
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
}
/* We can raise a differed exception */
gen_op_float_check_status();
gen_helper_float_check_status();
}
/* mtfsf */
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
{
TCGv t0;
if (unlikely(!ctx->fpu_enabled)) {
GEN_EXCP_NO_FP(ctx);
return;
}
gen_optimize_fprf();
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
gen_reset_fpstatus();
gen_op_store_fpscr(FM(ctx->opcode));
t0 = tcg_const_i32(FM(ctx->opcode));
gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
tcg_temp_free(t0);
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
}
/* We can raise a differed exception */
gen_op_float_check_status();
gen_helper_float_check_status();
}
/* mtfsfi */
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
{
int bf, sh;
TCGv t0, t1;
if (unlikely(!ctx->fpu_enabled)) {
GEN_EXCP_NO_FP(ctx);
@ -2430,14 +2430,17 @@ GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
bf = crbD(ctx->opcode) >> 2;
sh = 7 - bf;
gen_optimize_fprf();
tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh));
gen_reset_fpstatus();
gen_op_store_fpscr(1 << sh);
t0 = tcg_const_tl(FPIMM(ctx->opcode) << (4 * sh));
t1 = tcg_const_i32(1 << sh);
gen_helper_store_fpscr(t0, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
}
/* We can raise a differed exception */
gen_op_float_check_status();
gen_helper_float_check_status();
}
/*** Addressing modes ***/