armv7m_nvic: Implement ICSR without using internal GIC state
Change the implementation of the Interrupt Control and State Register in the v7M NVIC to not use the running_irq and last_active internal state fields in the GIC. These fields don't correspond to state in a real GIC and will be removed soon. The changes to the ICSR are: * the VECTACTIVE field is documented as identical to the IPSR[8:0] field, so implement it that way * implement RETTOBASE via looking at the active state bits Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1438089748-5528-2-git-send-email-peter.maydell@linaro.org
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@ -185,26 +185,25 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
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return cpu->midr;
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return cpu->midr;
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case 0xd04: /* Interrupt Control State. */
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case 0xd04: /* Interrupt Control State. */
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/* VECTACTIVE */
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/* VECTACTIVE */
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val = s->gic.running_irq[0];
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cpu = ARM_CPU(current_cpu);
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val = cpu->env.v7m.exception;
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if (val == 1023) {
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if (val == 1023) {
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val = 0;
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val = 0;
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} else if (val >= 32) {
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} else if (val >= 32) {
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val -= 16;
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val -= 16;
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}
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}
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/* RETTOBASE */
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if (s->gic.running_irq[0] == 1023
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|| s->gic.last_active[s->gic.running_irq[0]][0] == 1023) {
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val |= (1 << 11);
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}
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/* VECTPENDING */
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/* VECTPENDING */
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if (s->gic.current_pending[0] != 1023)
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if (s->gic.current_pending[0] != 1023)
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val |= (s->gic.current_pending[0] << 12);
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val |= (s->gic.current_pending[0] << 12);
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/* ISRPENDING */
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/* ISRPENDING and RETTOBASE */
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for (irq = 32; irq < s->num_irq; irq++) {
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for (irq = 32; irq < s->num_irq; irq++) {
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if (s->gic.irq_state[irq].pending) {
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if (s->gic.irq_state[irq].pending) {
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val |= (1 << 22);
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val |= (1 << 22);
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break;
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break;
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}
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}
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if (irq != cpu->env.v7m.exception && s->gic.irq_state[irq].active) {
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val |= (1 << 11);
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}
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}
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}
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/* PENDSTSET */
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/* PENDSTSET */
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if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
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if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
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