vfio-pci: Test device reset capabilities
Not all resets are created equal. PM reset is not very reliable, especially for GPUs, so we might want to opt for a bus reset if a standard reset will only do a D3hot->D0 transition. We can also use this to tell if the standard reset will do a bus reset (if neither has_pm_reset or has_flr is probed, but the device still supports reset). Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
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					@ -185,6 +185,8 @@ typedef struct VFIODevice {
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    bool reset_works;
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					    bool reset_works;
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    bool has_vga;
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					    bool has_vga;
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    bool pci_aer;
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					    bool pci_aer;
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					    bool has_flr;
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					    bool has_pm_reset;
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} VFIODevice;
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					} VFIODevice;
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typedef struct VFIOGroup {
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					typedef struct VFIOGroup {
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					@ -2513,6 +2515,42 @@ static int vfio_setup_pcie_cap(VFIODevice *vdev, int pos, uint8_t size)
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    return pos;
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					    return pos;
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}
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					}
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					static void vfio_check_pcie_flr(VFIODevice *vdev, uint8_t pos)
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					{
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					    uint32_t cap = pci_get_long(vdev->pdev.config + pos + PCI_EXP_DEVCAP);
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					    if (cap & PCI_EXP_DEVCAP_FLR) {
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					        DPRINTF("%04x:%02x:%02x.%x Supports FLR via PCIe cap\n",
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					                vdev->host.domain, vdev->host.bus, vdev->host.slot,
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					                vdev->host.function);
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					        vdev->has_flr = true;
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					    }
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					}
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					static void vfio_check_pm_reset(VFIODevice *vdev, uint8_t pos)
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					{
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					    uint16_t csr = pci_get_word(vdev->pdev.config + pos + PCI_PM_CTRL);
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					    if (!(csr & PCI_PM_CTRL_NO_SOFT_RESET)) {
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					        DPRINTF("%04x:%02x:%02x.%x Supports PM reset\n",
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					                vdev->host.domain, vdev->host.bus, vdev->host.slot,
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					                vdev->host.function);
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					        vdev->has_pm_reset = true;
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					    }
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					}
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					static void vfio_check_af_flr(VFIODevice *vdev, uint8_t pos)
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					{
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					    uint8_t cap = pci_get_byte(vdev->pdev.config + pos + PCI_AF_CAP);
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					    if ((cap & PCI_AF_CAP_TP) && (cap & PCI_AF_CAP_FLR)) {
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					        DPRINTF("%04x:%02x:%02x.%x Supports FLR via AF cap\n",
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					                vdev->host.domain, vdev->host.bus, vdev->host.slot,
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					                vdev->host.function);
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					        vdev->has_flr = true;
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					    }
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					}
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static int vfio_add_std_cap(VFIODevice *vdev, uint8_t pos)
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					static int vfio_add_std_cap(VFIODevice *vdev, uint8_t pos)
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{
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					{
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    PCIDevice *pdev = &vdev->pdev;
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					    PCIDevice *pdev = &vdev->pdev;
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					@ -2557,13 +2595,21 @@ static int vfio_add_std_cap(VFIODevice *vdev, uint8_t pos)
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        ret = vfio_setup_msi(vdev, pos);
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					        ret = vfio_setup_msi(vdev, pos);
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        break;
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					        break;
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    case PCI_CAP_ID_EXP:
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					    case PCI_CAP_ID_EXP:
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					        vfio_check_pcie_flr(vdev, pos);
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        ret = vfio_setup_pcie_cap(vdev, pos, size);
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					        ret = vfio_setup_pcie_cap(vdev, pos, size);
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        break;
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					        break;
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    case PCI_CAP_ID_MSIX:
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					    case PCI_CAP_ID_MSIX:
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        ret = vfio_setup_msix(vdev, pos);
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					        ret = vfio_setup_msix(vdev, pos);
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        break;
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					        break;
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    case PCI_CAP_ID_PM:
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					    case PCI_CAP_ID_PM:
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					        vfio_check_pm_reset(vdev, pos);
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        vdev->pm_cap = pos;
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					        vdev->pm_cap = pos;
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					        ret = pci_add_capability(pdev, cap_id, pos, size);
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					        break;
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					    case PCI_CAP_ID_AF:
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					        vfio_check_af_flr(vdev, pos);
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					        ret = pci_add_capability(pdev, cap_id, pos, size);
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					        break;
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    default:
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					    default:
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        ret = pci_add_capability(pdev, cap_id, pos, size);
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					        ret = pci_add_capability(pdev, cap_id, pos, size);
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        break;
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					        break;
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