i8259: Eliminate PicState2
Introduce a reference to the slave PIC for the few cases we need to access it without a proper pointer at hand and drop PicState2. We could even live without slave_pic if we had a better way of modeling the cascade bus the PICs are attached to (in addition to the ISA bus). Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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								hw/i8259.c
								
								
								
								
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			@ -40,7 +40,7 @@
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//#define DEBUG_IRQ_LATENCY
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//#define DEBUG_IRQ_COUNT
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typedef struct PicState {
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struct PicState {
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    uint8_t last_irr; /* edge detection */
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    uint8_t irr; /* interrupt request register */
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    uint8_t imr; /* interrupt mask register */
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			@ -62,13 +62,6 @@ typedef struct PicState {
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    bool master; /* reflects /SP input pin */
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    MemoryRegion base_io;
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    MemoryRegion elcr_io;
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} PicState;
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struct PicState2 {
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    /* 0 is master pic, 1 is slave pic */
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    /* XXX: better separation between the two pics */
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    PicState pics[2];
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    void *irq_request_opaque;
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};
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#if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
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			@ -77,7 +70,8 @@ static int irq_level[16];
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#ifdef DEBUG_IRQ_COUNT
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static uint64_t irq_count[16];
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#endif
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PicState2 *isa_pic;
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PicState *isa_pic;
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static PicState *slave_pic;
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/* return the highest priority found in mask (highest = smallest
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   number). Return 8 if no irq */
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			@ -168,7 +162,7 @@ int64_t irq_time[16];
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static void i8259_set_irq(void *opaque, int irq, int level)
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{
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    PicState2 *s = opaque;
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    PicState *s = irq <= 7 ? isa_pic : slave_pic;
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#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
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    if (level != irq_level[irq]) {
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			@ -185,7 +179,7 @@ static void i8259_set_irq(void *opaque, int irq, int level)
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        irq_time[irq] = qemu_get_clock_ns(vm_clock);
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    }
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#endif
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    pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
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    pic_set_irq1(s, irq & 7, level);
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}
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/* acknowledge interrupt 'irq' */
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			@ -203,29 +197,29 @@ static void pic_intack(PicState *s, int irq)
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    pic_update_irq(s);
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}
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int pic_read_irq(PicState2 *s)
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int pic_read_irq(PicState *s)
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{
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    int irq, irq2, intno;
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    irq = pic_get_irq(&s->pics[0]);
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    irq = pic_get_irq(s);
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    if (irq >= 0) {
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        if (irq == 2) {
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            irq2 = pic_get_irq(&s->pics[1]);
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            irq2 = pic_get_irq(slave_pic);
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            if (irq2 >= 0) {
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                pic_intack(&s->pics[1], irq2);
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                pic_intack(slave_pic, irq2);
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            } else {
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                /* spurious IRQ on slave controller */
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                irq2 = 7;
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            }
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            intno = s->pics[1].irq_base + irq2;
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            intno = slave_pic->irq_base + irq2;
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        } else {
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            intno = s->pics[0].irq_base + irq;
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            intno = s->irq_base + irq;
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        }
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        pic_intack(&s->pics[0], irq);
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        pic_intack(s, irq);
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    } else {
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        /* spurious IRQ on host controller */
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        irq = 7;
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        intno = s->pics[0].irq_base + irq;
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        intno = s->irq_base + irq;
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    }
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#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
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			@ -390,9 +384,9 @@ static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr,
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    return ret;
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}
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int pic_get_output(PicState2 *s)
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int pic_get_output(PicState *s)
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{
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    return (pic_get_irq(&s->pics[0]) >= 0);
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    return (pic_get_irq(s) >= 0);
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}
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static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
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			@ -480,8 +474,8 @@ void pic_info(Monitor *mon)
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    if (!isa_pic)
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        return;
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    for(i=0;i<2;i++) {
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        s = &isa_pic->pics[i];
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    for (i = 0; i < 2; i++) {
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        s = i == 0 ? isa_pic : slave_pic;
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        monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
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                       "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
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                       i, s->irr, s->imr, s->isr, s->priority_add,
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			@ -510,14 +504,19 @@ void irq_info(Monitor *mon)
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qemu_irq *i8259_init(qemu_irq parent_irq)
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{
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    qemu_irq *irqs;
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    PicState2 *s;
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    PicState *s;
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    s = g_malloc0(sizeof(PicState2));
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    irqs = qemu_allocate_irqs(i8259_set_irq, s, 16);
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    pic_init(0x20, 0x4d0, &s->pics[0], parent_irq, true);
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    pic_init(0xa0, 0x4d1, &s->pics[1], irqs[2], false);
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    s->pics[0].elcr_mask = 0xf8;
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    s->pics[1].elcr_mask = 0xde;
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    irqs = qemu_allocate_irqs(i8259_set_irq, NULL, 16);
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    s = g_malloc0(sizeof(PicState));
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    pic_init(0x20, 0x4d0, s, parent_irq, true);
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    s->elcr_mask = 0xf8;
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    isa_pic = s;
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    s = g_malloc0(sizeof(PicState));
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    pic_init(0xa0, 0x4d1, s, irqs[2], false);
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    s->elcr_mask = 0xde;
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    slave_pic = s;
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    return irqs;
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}
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										8
									
								
								hw/pc.h
								
								
								
								
							
							
						
						
									
										8
									
								
								hw/pc.h
								
								
								
								
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			@ -60,11 +60,11 @@ bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
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/* i8259.c */
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typedef struct PicState2 PicState2;
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extern PicState2 *isa_pic;
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typedef struct PicState PicState;
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extern PicState *isa_pic;
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qemu_irq *i8259_init(qemu_irq parent_irq);
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int pic_read_irq(PicState2 *s);
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int pic_get_output(PicState2 *s);
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int pic_read_irq(PicState *s);
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int pic_get_output(PicState *s);
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void pic_info(Monitor *mon);
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void irq_info(Monitor *mon);
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