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hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io 

(qemu) info mtree
 address-space: cpu-memory-0
   0000000000000000-ffffffffffffffff (prio 0, i/o): system
     0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom
-    000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io
+    000000001e600000-000000001e7fffff (prio -1000, i/o): aspeed_soc.io
     000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc
     000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1
     000000001e631000-000000001e6310ff (prio 0, i/o): aspeed.smc.ast2500-spi2

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 20180209085755.30414-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2018-02-15 18:29:36 +00:00 committed by Peter Maydell
parent 022d72d0b1
commit c7c3c9f8d0
2 changed files with 3 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
hw/arm/aspeed_soc.c
View File

@ -15,6 +15,7 @@
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h" #include "hw/arm/aspeed_soc.h"
#include "hw/char/serial.h" #include "hw/char/serial.h"
#include "qemu/log.h" #include "qemu/log.h"
@ -99,31 +100,6 @@ static const AspeedSoCInfo aspeed_socs[] = {
}, },
}; };
/*
* IO handlers: simply catch any reads/writes to IO addresses that aren't
* handled by a device mapping.
*/
static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)
{
qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
__func__, offset, size);
return 0;
}
static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
__func__, offset, value, size);
}
static const MemoryRegionOps aspeed_soc_io_ops = {
.read = aspeed_soc_io_read,
.write = aspeed_soc_io_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void aspeed_soc_init(Object *obj) static void aspeed_soc_init(Object *obj)
{ {
AspeedSoCState *s = ASPEED_SOC(obj); AspeedSoCState *s = ASPEED_SOC(obj);
@ -199,10 +175,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
Error *err = NULL, *local_err = NULL; Error *err = NULL, *local_err = NULL;
/* IO space */ /* IO space */
memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL, create_unimplemented_device("aspeed_soc.io",
"aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE); ASPEED_SOC_IOMEM_BASE, ASPEED_SOC_IOMEM_SIZE);
memory_region_add_subregion_overlap(get_system_memory(),
ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);
/* CPU */ /* CPU */
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);

1
include/hw/arm/aspeed_soc.h
View File

@ -31,7 +31,6 @@ typedef struct AspeedSoCState {
/*< public >*/ /*< public >*/
ARMCPU cpu; ARMCPU cpu;
MemoryRegion iomem;
MemoryRegion sram; MemoryRegion sram;
AspeedVICState vic; AspeedVICState vic;
AspeedTimerCtrlState timerctrl; AspeedTimerCtrlState timerctrl;