libqos: add PPC64 PCI support
Signed-off-by: Laurent Vivier <lvivier@redhat.com> [dwg: Fixed build problem on 32-bit hosts] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Laurent Vivier
David Gibson
parent
2020b67d85
commit
cf716b31cb
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@ -591,6 +591,7 @@ libqos-obj-y += tests/libqos/i2c.o tests/libqos/libqos.o
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libqos-spapr-obj-y = $(libqos-obj-y) tests/libqos/malloc-spapr.o
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libqos-spapr-obj-y += tests/libqos/libqos-spapr.o
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libqos-spapr-obj-y += tests/libqos/rtas.o
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libqos-spapr-obj-y += tests/libqos/pci-spapr.o
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libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o
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libqos-pc-obj-y += tests/libqos/malloc-pc.o tests/libqos/libqos-pc.o
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libqos-pc-obj-y += tests/libqos/ahci.o
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@ -255,28 +255,6 @@ void qpci_free_pc(QPCIBus *bus)
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g_free(s);
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}
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void qpci_plug_device_test(const char *driver, const char *id,
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uint8_t slot, const char *opts)
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{
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QDict *response;
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char *cmd;
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cmd = g_strdup_printf("{'execute': 'device_add',"
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" 'arguments': {"
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" 'driver': '%s',"
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" 'addr': '%d',"
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" %s%s"
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" 'id': '%s'"
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"}}", driver, slot,
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opts ? opts : "", opts ? "," : "",
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id);
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response = qmp(cmd);
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g_free(cmd);
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g_assert(response);
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g_assert(!qdict_haskey(response, "error"));
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QDECREF(response);
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}
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void qpci_unplug_acpi_device_test(const char *id, uint8_t slot)
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{
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QDict *response;
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@ -0,0 +1,288 @@
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/*
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* libqos PCI bindings for SPAPR
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#include "libqos/pci-spapr.h"
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#include "libqos/rtas.h"
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#include "hw/pci/pci_regs.h"
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#include "qemu-common.h"
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#include "qemu/host-utils.h"
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/* From include/hw/pci-host/spapr.h */
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#define SPAPR_PCI_BASE_BUID 0x800000020000000ULL
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#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
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#define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL
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#define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL
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#define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000
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#define SPAPR_PCI_MMIO_WIN_SIZE (SPAPR_PCI_WINDOW_SPACING - \
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SPAPR_PCI_MEM_WIN_BUS_OFFSET)
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#define SPAPR_PCI_IO_WIN_OFF 0x80000000
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#define SPAPR_PCI_IO_WIN_SIZE 0x10000
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/* index is the phb index */
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#define BUIDBASE(index) (SPAPR_PCI_BASE_BUID + (index))
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#define PCIBASE(index) (SPAPR_PCI_WINDOW_BASE + \
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(index) * SPAPR_PCI_WINDOW_SPACING)
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#define IOBASE(index) (PCIBASE(index) + SPAPR_PCI_IO_WIN_OFF)
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#define MMIOBASE(index) (PCIBASE(index) + SPAPR_PCI_MMIO_WIN_OFF)
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typedef struct QPCIBusSPAPR {
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QPCIBus bus;
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QGuestAllocator *alloc;
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uint64_t pci_hole_start;
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uint64_t pci_hole_size;
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uint64_t pci_hole_alloc;
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uint32_t pci_iohole_start;
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uint32_t pci_iohole_size;
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uint32_t pci_iohole_alloc;
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} QPCIBusSPAPR;
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/*
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* PCI devices are always little-endian
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* SPAPR by default is big-endian
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* so PCI accessors need to swap data endianness
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*/
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static uint8_t qpci_spapr_io_readb(QPCIBus *bus, void *addr)
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{
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uint64_t port = (uintptr_t)addr;
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uint8_t v;
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if (port < SPAPR_PCI_IO_WIN_SIZE) {
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v = readb(IOBASE(0) + port);
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} else {
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v = readb(MMIOBASE(0) + port);
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}
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return v;
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}
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static uint16_t qpci_spapr_io_readw(QPCIBus *bus, void *addr)
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{
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uint64_t port = (uintptr_t)addr;
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uint16_t v;
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if (port < SPAPR_PCI_IO_WIN_SIZE) {
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v = readw(IOBASE(0) + port);
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} else {
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v = readw(MMIOBASE(0) + port);
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}
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return bswap16(v);
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}
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static uint32_t qpci_spapr_io_readl(QPCIBus *bus, void *addr)
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{
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uint64_t port = (uintptr_t)addr;
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uint32_t v;
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if (port < SPAPR_PCI_IO_WIN_SIZE) {
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v = readl(IOBASE(0) + port);
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} else {
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v = readl(MMIOBASE(0) + port);
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}
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return bswap32(v);
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}
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static void qpci_spapr_io_writeb(QPCIBus *bus, void *addr, uint8_t value)
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{
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uint64_t port = (uintptr_t)addr;
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if (port < SPAPR_PCI_IO_WIN_SIZE) {
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writeb(IOBASE(0) + port, value);
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} else {
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writeb(MMIOBASE(0) + port, value);
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}
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}
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static void qpci_spapr_io_writew(QPCIBus *bus, void *addr, uint16_t value)
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{
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uint64_t port = (uintptr_t)addr;
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value = bswap16(value);
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if (port < SPAPR_PCI_IO_WIN_SIZE) {
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writew(IOBASE(0) + port, value);
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} else {
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writew(MMIOBASE(0) + port, value);
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}
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}
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static void qpci_spapr_io_writel(QPCIBus *bus, void *addr, uint32_t value)
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{
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uint64_t port = (uintptr_t)addr;
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value = bswap32(value);
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if (port < SPAPR_PCI_IO_WIN_SIZE) {
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writel(IOBASE(0) + port, value);
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} else {
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writel(MMIOBASE(0) + port, value);
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}
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}
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static uint8_t qpci_spapr_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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return qrtas_ibm_read_pci_config(s->alloc, BUIDBASE(0),
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config_addr, 1);
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}
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static uint16_t qpci_spapr_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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return qrtas_ibm_read_pci_config(s->alloc, BUIDBASE(0),
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config_addr, 2);
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}
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static uint32_t qpci_spapr_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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return qrtas_ibm_read_pci_config(s->alloc, BUIDBASE(0),
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config_addr, 4);
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}
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static void qpci_spapr_config_writeb(QPCIBus *bus, int devfn, uint8_t offset,
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uint8_t value)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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qrtas_ibm_write_pci_config(s->alloc, BUIDBASE(0),
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config_addr, 1, value);
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}
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static void qpci_spapr_config_writew(QPCIBus *bus, int devfn, uint8_t offset,
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uint16_t value)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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qrtas_ibm_write_pci_config(s->alloc, BUIDBASE(0),
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config_addr, 2, value);
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}
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static void qpci_spapr_config_writel(QPCIBus *bus, int devfn, uint8_t offset,
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uint32_t value)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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qrtas_ibm_write_pci_config(s->alloc, BUIDBASE(0),
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config_addr, 4, value);
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}
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static void *qpci_spapr_iomap(QPCIBus *bus, QPCIDevice *dev, int barno,
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uint64_t *sizeptr)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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static const int bar_reg_map[] = {
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PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
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PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
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};
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int bar_reg;
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uint32_t addr;
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uint64_t size;
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uint32_t io_type;
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g_assert(barno >= 0 && barno <= 5);
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bar_reg = bar_reg_map[barno];
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qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
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addr = qpci_config_readl(dev, bar_reg);
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io_type = addr & PCI_BASE_ADDRESS_SPACE;
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if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
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addr &= PCI_BASE_ADDRESS_IO_MASK;
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} else {
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addr &= PCI_BASE_ADDRESS_MEM_MASK;
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}
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size = (1ULL << ctzl(addr));
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if (size == 0) {
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return NULL;
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}
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if (sizeptr) {
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*sizeptr = size;
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}
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if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
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uint16_t loc;
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g_assert(QEMU_ALIGN_UP(s->pci_iohole_alloc, size) + size
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<= s->pci_iohole_size);
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s->pci_iohole_alloc = QEMU_ALIGN_UP(s->pci_iohole_alloc, size);
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loc = s->pci_iohole_start + s->pci_iohole_alloc;
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s->pci_iohole_alloc += size;
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qpci_config_writel(dev, bar_reg, loc | PCI_BASE_ADDRESS_SPACE_IO);
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return (void *)(unsigned long)loc;
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} else {
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uint64_t loc;
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g_assert(QEMU_ALIGN_UP(s->pci_hole_alloc, size) + size
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<= s->pci_hole_size);
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s->pci_hole_alloc = QEMU_ALIGN_UP(s->pci_hole_alloc, size);
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loc = s->pci_hole_start + s->pci_hole_alloc;
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s->pci_hole_alloc += size;
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qpci_config_writel(dev, bar_reg, loc);
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return (void *)(unsigned long)loc;
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}
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}
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static void qpci_spapr_iounmap(QPCIBus *bus, void *data)
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{
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/* FIXME */
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}
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QPCIBus *qpci_init_spapr(QGuestAllocator *alloc)
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{
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QPCIBusSPAPR *ret;
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ret = g_malloc(sizeof(*ret));
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ret->alloc = alloc;
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ret->bus.io_readb = qpci_spapr_io_readb;
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ret->bus.io_readw = qpci_spapr_io_readw;
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ret->bus.io_readl = qpci_spapr_io_readl;
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ret->bus.io_writeb = qpci_spapr_io_writeb;
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ret->bus.io_writew = qpci_spapr_io_writew;
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ret->bus.io_writel = qpci_spapr_io_writel;
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ret->bus.config_readb = qpci_spapr_config_readb;
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ret->bus.config_readw = qpci_spapr_config_readw;
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ret->bus.config_readl = qpci_spapr_config_readl;
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ret->bus.config_writeb = qpci_spapr_config_writeb;
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ret->bus.config_writew = qpci_spapr_config_writew;
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ret->bus.config_writel = qpci_spapr_config_writel;
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ret->bus.iomap = qpci_spapr_iomap;
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ret->bus.iounmap = qpci_spapr_iounmap;
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ret->pci_hole_start = 0xC0000000;
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ret->pci_hole_size = SPAPR_PCI_MMIO_WIN_SIZE;
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ret->pci_hole_alloc = 0;
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ret->pci_iohole_start = 0xc000;
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ret->pci_iohole_size = SPAPR_PCI_IO_WIN_SIZE;
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ret->pci_iohole_alloc = 0;
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return &ret->bus;
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}
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void qpci_free_spapr(QPCIBus *bus)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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g_free(s);
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}
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@ -0,0 +1,17 @@
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/*
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* libqos PCI bindings for SPAPR
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef LIBQOS_PCI_SPAPR_H
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#define LIBQOS_PCI_SPAPR_H
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#include "libqos/malloc.h"
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#include "libqos/pci.h"
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QPCIBus *qpci_init_spapr(QGuestAllocator *alloc);
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void qpci_free_spapr(QPCIBus *bus);
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#endif
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@ -263,4 +263,24 @@ void qpci_iounmap(QPCIDevice *dev, void *data)
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dev->bus->iounmap(dev->bus, data);
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}
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void qpci_plug_device_test(const char *driver, const char *id,
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uint8_t slot, const char *opts)
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{
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QDict *response;
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char *cmd;
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cmd = g_strdup_printf("{'execute': 'device_add',"
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" 'arguments': {"
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" 'driver': '%s',"
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" 'addr': '%d',"
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" %s%s"
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" 'id': '%s'"
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"}}", driver, slot,
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opts ? opts : "", opts ? "," : "",
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id);
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response = qmp(cmd);
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g_free(cmd);
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g_assert(response);
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g_assert(!qdict_haskey(response, "error"));
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QDECREF(response);
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}
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@ -69,3 +69,48 @@ int qrtas_get_time_of_day(QGuestAllocator *alloc, struct tm *tm, uint32_t *ns)
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return res;
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}
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uint32_t qrtas_ibm_read_pci_config(QGuestAllocator *alloc, uint64_t buid,
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uint32_t addr, uint32_t size)
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{
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int res;
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uint32_t args[4], ret[2];
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args[0] = addr;
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args[1] = buid >> 32;
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args[2] = buid & 0xffffffff;
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args[3] = size;
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res = qrtas_call(alloc, "ibm,read-pci-config", 4, args, 2, ret);
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if (res != 0) {
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return -1;
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}
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if (ret[0] != 0) {
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return -1;
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}
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return ret[1];
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}
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int qrtas_ibm_write_pci_config(QGuestAllocator *alloc, uint64_t buid,
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uint32_t addr, uint32_t size, uint32_t val)
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{
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int res;
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uint32_t args[5], ret[1];
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args[0] = addr;
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args[1] = buid >> 32;
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args[2] = buid & 0xffffffff;
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args[3] = size;
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args[4] = val;
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res = qrtas_call(alloc, "ibm,write-pci-config", 5, args, 1, ret);
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if (res != 0) {
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return -1;
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}
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if (ret[0] != 0) {
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return -1;
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}
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return 0;
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}
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@ -8,4 +8,8 @@
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#include "libqos/malloc.h"
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int qrtas_get_time_of_day(QGuestAllocator *alloc, struct tm *tm, uint32_t *ns);
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uint32_t qrtas_ibm_read_pci_config(QGuestAllocator *alloc, uint64_t buid,
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uint32_t addr, uint32_t size);
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int qrtas_ibm_write_pci_config(QGuestAllocator *alloc, uint64_t buid,
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uint32_t addr, uint32_t size, uint32_t val);
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#endif /* LIBQOS_RTAS_H */
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Reference in New Issue