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target-arm: Fix aarch64 vec_reg_offset 

Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used
for a big-endian host doesn't do what's intended.  Fix this by adding
in the vfp.regs offset after computing the inter-register offset.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-id: 1481085020-2614-2-git-send-email-rth@twiddle.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 416d72b97b)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
This commit is contained in:
Richard Henderson 2016-12-27 14:59:24 +00:00 committed by Michael Roth
parent 74b13f92c2
commit d437262fa8
1 changed files with 2 additions and 1 deletions
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3
target-arm/translate-a64.c
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@ -527,7 +527,7 @@ static inline void assert_fp_access_checked(DisasContext *s)
static inline int vec_reg_offset(DisasContext *s, int regno, static inline int vec_reg_offset(DisasContext *s, int regno,
int element, TCGMemOp size) int element, TCGMemOp size)
{ {
int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); int offs = 0;
#ifdef HOST_WORDS_BIGENDIAN #ifdef HOST_WORDS_BIGENDIAN
/* This is complicated slightly because vfp.regs[2n] is /* This is complicated slightly because vfp.regs[2n] is
* still the low half and vfp.regs[2n+1] the high half * still the low half and vfp.regs[2n+1] the high half
@ -540,6 +540,7 @@ static inline int vec_reg_offset(DisasContext *s, int regno,
#else #else
offs += element * (1 << size); offs += element * (1 << size);
#endif #endif
offs += offsetof(CPUARMState, vfp.regs[regno * 2]);
assert_fp_access_checked(s); assert_fp_access_checked(s);
return offs; return offs;
} }