falso
/
qemu-irix
mirror of https://github.com/n64decomp/qemu-irix.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

xilinx-ethlite: Simplify byteswapping to/from brams 

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
This commit is contained in:
Edgar E. Iglesias 2011-03-10 09:16:52 +01:00
parent b651fc6fd8
commit d48751ed4f
1 changed files with 2 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
hw/xilinx_ethlite.c
View File

@ -90,13 +90,8 @@ static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
D(qemu_log("%s %x=%x\n", __func__, addr * 4, r));
break;
/* Rx packet data is endian fixed at the way into the rx rams. This
* speeds things up because the ethlite MAC does not have a len
* register. That means the CPU will issue MMIO reads for the entire
* 2k rx buffer even for small packets.
*/
default:
r = s->regs[addr];
r = tswap32(s->regs[addr]);
break;
}
return r;
@ -145,9 +140,8 @@ eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
s->regs[addr] = value;
break;
/* Packet data, make sure it stays BE. */
default:
s->regs[addr] = cpu_to_be32(value);
s->regs[addr] = tswap32(value);
break;
}
}
@ -172,7 +166,6 @@ static ssize_t eth_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
{
struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
unsigned int rxbase = s->rxbuf * (0x800 / 4);
int i;
/* DA filter. */
if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
@ -186,12 +179,6 @@ static ssize_t eth_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
D(qemu_log("%s %d rxbase=%x\n", __func__, size, rxbase));
memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
/* Bring it into host endianess. */
for (i = 0; i < ((size + 3) / 4); i++) {
uint32_t d = s->regs[rxbase + R_RX_BUF0 + i];
s->regs[rxbase + R_RX_BUF0 + i] = be32_to_cpu(d);
}
s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I)
eth_pulse_irq(s);