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Convert sub 

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2009-05-10 10:38:34 +03:00
parent 38482a77f0
commit d4b0d46898
2 changed files with 83 additions and 37 deletions
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72
target-sparc/op_helper.c
View File

@ -902,6 +902,76 @@ static uint32_t compute_C_addx_xcc(void)
}
#endif
static inline uint32_t get_C_sub_icc(target_ulong src1, target_ulong src2)
{
uint32_t ret = 0;
if ((src1 & 0xffffffffULL) < (src2 & 0xffffffffULL))
ret |= PSR_CARRY;
return ret;
}
static inline uint32_t get_V_sub_icc(target_ulong dst, target_ulong src1,
target_ulong src2)
{
uint32_t ret = 0;
if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 31))
ret |= PSR_OVF;
return ret;
}
static uint32_t compute_all_sub(void)
{
uint32_t ret;
ret = get_NZ_icc(CC_DST);
ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
return ret;
}
static uint32_t compute_C_sub(void)
{
return get_C_sub_icc(CC_SRC, CC_SRC2);
}
#ifdef TARGET_SPARC64
static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2)
{
uint32_t ret = 0;
if (src1 < src2)
ret |= PSR_CARRY;
return ret;
}
static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1,
target_ulong src2)
{
uint32_t ret = 0;
if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 63))
ret |= PSR_OVF;
return ret;
}
static uint32_t compute_all_sub_xcc(void)
{
uint32_t ret;
ret = get_NZ_xcc(CC_DST);
ret |= get_C_sub_xcc(CC_SRC, CC_SRC2);
ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
return ret;
}
static uint32_t compute_C_sub_xcc(void)
{
return get_C_sub_xcc(CC_SRC, CC_SRC2);
}
#endif
static uint32_t compute_all_logic(void)
{
return get_NZ_icc(CC_DST);
@ -929,6 +999,7 @@ static const CCTable icc_table[CC_OP_NB] = {
[CC_OP_FLAGS] = { compute_all_flags, compute_C_flags },
[CC_OP_ADD] = { compute_all_add, compute_C_add },
[CC_OP_ADDX] = { compute_all_addx, compute_C_addx },
[CC_OP_SUB] = { compute_all_sub, compute_C_sub },
[CC_OP_LOGIC] = { compute_all_logic, compute_C_logic },
};
@ -938,6 +1009,7 @@ static const CCTable xcc_table[CC_OP_NB] = {
[CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc },
[CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc },
[CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc },
[CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
[CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic },
};
#endif

48
target-sparc/translate.c
View File

@ -432,18 +432,6 @@ static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
gen_set_label(l1);
}
static inline void gen_op_logic_cc(TCGv dst)
{
tcg_gen_mov_tl(cpu_cc_dst, dst);
gen_cc_clear_icc();
gen_cc_NZ_icc(cpu_cc_dst);
#ifdef TARGET_SPARC64
gen_cc_clear_xcc();
gen_cc_NZ_xcc(cpu_cc_dst);
#endif
}
static inline void gen_tag_tv(TCGv src1, TCGv src2)
{
int l1;
@ -623,32 +611,20 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
tcg_temp_free(r_temp);
}
static inline void gen_op_sub_cc2(TCGv dst)
{
gen_cc_clear_icc();
gen_cc_NZ_icc(cpu_cc_dst);
gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#ifdef TARGET_SPARC64
gen_cc_clear_xcc();
gen_cc_NZ_xcc(cpu_cc_dst);
gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#endif
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2)
static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc)
{
tcg_gen_mov_tl(cpu_cc_src, src1);
tcg_gen_movi_tl(cpu_cc_src2, src2);
if (src2 == 0) {
tcg_gen_mov_tl(dst, src1);
gen_op_logic_cc(dst);
tcg_gen_mov_tl(cpu_cc_dst, src1);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
dc->cc_op = CC_OP_LOGIC;
} else {
tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2);
gen_op_sub_cc2(dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
dc->cc_op = CC_OP_SUB;
}
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
@ -656,7 +632,7 @@ static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_mov_tl(cpu_cc_src, src1);
tcg_gen_mov_tl(cpu_cc_src2, src2);
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
gen_op_sub_cc2(dst);
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
static inline void gen_op_subx_cc2(TCGv dst)
@ -3171,17 +3147,15 @@ static void disas_sparc_insn(DisasContext * dc)
if (IS_IMM) {
simm = GET_FIELDs(insn, 19, 31);
if (xop & 0x10) {
gen_op_subi_cc(cpu_dst, cpu_src1, simm);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
dc->cc_op = CC_OP_FLAGS;
gen_op_subi_cc(cpu_dst, cpu_src1, simm, dc);
} else {
tcg_gen_subi_tl(cpu_dst, cpu_src1, simm);
}
} else {
if (xop & 0x10) {
gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
dc->cc_op = CC_OP_FLAGS;
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
dc->cc_op = CC_OP_SUB;
} else {
tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
}