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pci-bridge: Turn PCIBridge into abstract QOM type 

Introduce TYPE_PCI_BRIDGE as base type and use PCI_BRIDGE() casts.

Reviewed-by: Don Koch <dkoch@verizon.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
[AF: Updated pbm-bridge parent to TYPE_PCI_BRIDGE]
Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2013-07-11 17:13:43 +02:00
parent 45c0a675f9
commit f055e96bd4
11 changed files with 78 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hw/pci-bridge/dec.c
View File

@ -74,7 +74,7 @@ static void dec_21154_pci_bridge_class_init(ObjectClass *klass, void *data)
static const TypeInfo dec_21154_pci_bridge_info = { static const TypeInfo dec_21154_pci_bridge_info = {
.name = "dec-21154-p2p-bridge", .name = "dec-21154-p2p-bridge",
.parent = TYPE_PCI_DEVICE, .parent = TYPE_PCI_BRIDGE,
.instance_size = sizeof(PCIBridge), .instance_size = sizeof(PCIBridge),
.class_init = dec_21154_pci_bridge_class_init, .class_init = dec_21154_pci_bridge_class_init,
}; };
@ -86,7 +86,7 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
dev = pci_create_multifunction(parent_bus, devfn, false, dev = pci_create_multifunction(parent_bus, devfn, false,
"dec-21154-p2p-bridge"); "dec-21154-p2p-bridge");
br = DO_UPCAST(PCIBridge, dev, dev); br = PCI_BRIDGE(dev);
pci_bridge_map_irq(br, "DEC 21154 PCI-PCI bridge", dec_map_irq); pci_bridge_map_irq(br, "DEC 21154 PCI-PCI bridge", dec_map_irq);
qdev_init_nofail(&dev->qdev); qdev_init_nofail(&dev->qdev);
return pci_bridge_get_sec_bus(br); return pci_bridge_get_sec_bus(br);

6
hw/pci-bridge/i82801b11.c
View File

@ -93,7 +93,7 @@ static void i82801b11_bridge_class_init(ObjectClass *klass, void *data)
static const TypeInfo i82801b11_bridge_info = { static const TypeInfo i82801b11_bridge_info = {
.name = "i82801b11-bridge", .name = "i82801b11-bridge",
.parent = TYPE_PCI_DEVICE, .parent = TYPE_PCI_BRIDGE,
.instance_size = sizeof(I82801b11Bridge), .instance_size = sizeof(I82801b11Bridge),
.class_init = i82801b11_bridge_class_init, .class_init = i82801b11_bridge_class_init,
}; };
@ -109,8 +109,8 @@ PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus)
if (!d) { if (!d) {
return NULL; return NULL;
} }
br = DO_UPCAST(PCIBridge, dev, d); br = PCI_BRIDGE(d);
qdev = &br->dev.qdev; qdev = DEVICE(d);
snprintf(buf, sizeof(buf), "pci.%d", sec_bus); snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
pci_bridge_map_irq(br, buf, pci_swizzle_map_irq_fn); pci_bridge_map_irq(br, buf, pci_swizzle_map_irq_fn);

18
hw/pci-bridge/ioh3420.c
View File

@ -92,7 +92,7 @@ static void ioh3420_reset(DeviceState *qdev)
static int ioh3420_initfn(PCIDevice *d) static int ioh3420_initfn(PCIDevice *d)
{ {
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); PCIBridge *br = PCI_BRIDGE(d);
PCIEPort *p = DO_UPCAST(PCIEPort, br, br); PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
PCIESlot *s = DO_UPCAST(PCIESlot, port, p); PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
int rc; int rc;
@ -148,7 +148,7 @@ err_bridge:
static void ioh3420_exitfn(PCIDevice *d) static void ioh3420_exitfn(PCIDevice *d)
{ {
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); PCIBridge *br = PCI_BRIDGE(d);
PCIEPort *p = DO_UPCAST(PCIEPort, br, br); PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
PCIESlot *s = DO_UPCAST(PCIESlot, port, p); PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
@ -171,9 +171,9 @@ PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,
if (!d) { if (!d) {
return NULL; return NULL;
} }
br = DO_UPCAST(PCIBridge, dev, d); br = PCI_BRIDGE(d);
qdev = &br->dev.qdev; qdev = DEVICE(d);
pci_bridge_map_irq(br, bus_name, map_irq); pci_bridge_map_irq(br, bus_name, map_irq);
qdev_prop_set_uint8(qdev, "port", port); qdev_prop_set_uint8(qdev, "port", port);
qdev_prop_set_uint8(qdev, "chassis", chassis); qdev_prop_set_uint8(qdev, "chassis", chassis);
@ -190,8 +190,8 @@ static const VMStateDescription vmstate_ioh3420 = {
.minimum_version_id_old = 1, .minimum_version_id_old = 1,
.post_load = pcie_cap_slot_post_load, .post_load = pcie_cap_slot_post_load,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), VMSTATE_PCIE_DEVICE(port.br.parent_obj, PCIESlot),
VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0, VMSTATE_STRUCT(port.br.parent_obj.exp.aer_log, PCIESlot, 0,
vmstate_pcie_aer_log, PCIEAERLog), vmstate_pcie_aer_log, PCIEAERLog),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
@ -202,8 +202,8 @@ static Property ioh3420_properties[] = {
DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
DEFINE_PROP_UINT16("aer_log_max", PCIESlot, DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
port.br.dev.exp.aer_log.log_max, port.br.parent_obj.exp.aer_log.log_max,
PCIE_AER_LOG_MAX_DEFAULT), PCIE_AER_LOG_MAX_DEFAULT),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };
@ -229,7 +229,7 @@ static void ioh3420_class_init(ObjectClass *klass, void *data)
static const TypeInfo ioh3420_info = { static const TypeInfo ioh3420_info = {
.name = "ioh3420", .name = "ioh3420",
.parent = TYPE_PCI_DEVICE, .parent = TYPE_PCI_BRIDGE,
.instance_size = sizeof(PCIESlot), .instance_size = sizeof(PCIESlot),
.class_init = ioh3420_class_init, .class_init = ioh3420_class_init,
}; };

10
hw/pci-bridge/pci_bridge_dev.c
View File

@ -38,7 +38,7 @@ typedef struct PCIBridgeDev PCIBridgeDev;
static int pci_bridge_dev_initfn(PCIDevice *dev) static int pci_bridge_dev_initfn(PCIDevice *dev)
{ {
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev); PCIBridge *br = PCI_BRIDGE(dev);
PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br); PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
int err; int err;
@ -81,7 +81,7 @@ bridge_error:
static void pci_bridge_dev_exitfn(PCIDevice *dev) static void pci_bridge_dev_exitfn(PCIDevice *dev)
{ {
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev); PCIBridge *br = PCI_BRIDGE(dev);
PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br); PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
if (msi_present(dev)) { if (msi_present(dev)) {
msi_uninit(dev); msi_uninit(dev);
@ -120,8 +120,8 @@ static Property pci_bridge_dev_properties[] = {
static const VMStateDescription pci_bridge_dev_vmstate = { static const VMStateDescription pci_bridge_dev_vmstate = {
.name = "pci_bridge", .name = "pci_bridge",
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(bridge.dev, PCIBridgeDev), VMSTATE_PCI_DEVICE(bridge.parent_obj, PCIBridgeDev),
SHPC_VMSTATE(bridge.dev.shpc, PCIBridgeDev), SHPC_VMSTATE(bridge.parent_obj.shpc, PCIBridgeDev),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
@ -146,7 +146,7 @@ static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
static const TypeInfo pci_bridge_dev_info = { static const TypeInfo pci_bridge_dev_info = {
.name = "pci-bridge", .name = "pci-bridge",
.parent = TYPE_PCI_DEVICE, .parent = TYPE_PCI_BRIDGE,
.instance_size = sizeof(PCIBridgeDev), .instance_size = sizeof(PCIBridgeDev),
.class_init = pci_bridge_dev_class_init, .class_init = pci_bridge_dev_class_init,
}; };

18
hw/pci-bridge/xio3130_downstream.c
View File

@ -56,7 +56,7 @@ static void xio3130_downstream_reset(DeviceState *qdev)
static int xio3130_downstream_initfn(PCIDevice *d) static int xio3130_downstream_initfn(PCIDevice *d)
{ {
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); PCIBridge *br = PCI_BRIDGE(d);
PCIEPort *p = DO_UPCAST(PCIEPort, br, br); PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
PCIESlot *s = DO_UPCAST(PCIESlot, port, p); PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
int rc; int rc;
@ -113,7 +113,7 @@ err_bridge:
static void xio3130_downstream_exitfn(PCIDevice *d) static void xio3130_downstream_exitfn(PCIDevice *d)
{ {
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); PCIBridge *br = PCI_BRIDGE(d);
PCIEPort *p = DO_UPCAST(PCIEPort, br, br); PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
PCIESlot *s = DO_UPCAST(PCIESlot, port, p); PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
@ -138,9 +138,9 @@ PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,
if (!d) { if (!d) {
return NULL; return NULL;
} }
br = DO_UPCAST(PCIBridge, dev, d); br = PCI_BRIDGE(d);
qdev = &br->dev.qdev; qdev = DEVICE(d);
pci_bridge_map_irq(br, bus_name, map_irq); pci_bridge_map_irq(br, bus_name, map_irq);
qdev_prop_set_uint8(qdev, "port", port); qdev_prop_set_uint8(qdev, "port", port);
qdev_prop_set_uint8(qdev, "chassis", chassis); qdev_prop_set_uint8(qdev, "chassis", chassis);
@ -157,8 +157,8 @@ static const VMStateDescription vmstate_xio3130_downstream = {
.minimum_version_id_old = 1, .minimum_version_id_old = 1,
.post_load = pcie_cap_slot_post_load, .post_load = pcie_cap_slot_post_load,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), VMSTATE_PCIE_DEVICE(port.br.parent_obj, PCIESlot),
VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0, VMSTATE_STRUCT(port.br.parent_obj.exp.aer_log, PCIESlot, 0,
vmstate_pcie_aer_log, PCIEAERLog), vmstate_pcie_aer_log, PCIEAERLog),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
@ -169,8 +169,8 @@ static Property xio3130_downstream_properties[] = {
DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
DEFINE_PROP_UINT16("aer_log_max", PCIESlot, DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
port.br.dev.exp.aer_log.log_max, port.br.parent_obj.exp.aer_log.log_max,
PCIE_AER_LOG_MAX_DEFAULT), PCIE_AER_LOG_MAX_DEFAULT),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };
@ -196,7 +196,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
static const TypeInfo xio3130_downstream_info = { static const TypeInfo xio3130_downstream_info = {
.name = "xio3130-downstream", .name = "xio3130-downstream",
.parent = TYPE_PCI_DEVICE, .parent = TYPE_PCI_BRIDGE,
.instance_size = sizeof(PCIESlot), .instance_size = sizeof(PCIESlot),
.class_init = xio3130_downstream_class_init, .class_init = xio3130_downstream_class_init,
}; };

19
hw/pci-bridge/xio3130_upstream.c
View File

@ -53,7 +53,7 @@ static void xio3130_upstream_reset(DeviceState *qdev)
static int xio3130_upstream_initfn(PCIDevice *d) static int xio3130_upstream_initfn(PCIDevice *d)
{ {
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); PCIBridge *br = PCI_BRIDGE(d);
PCIEPort *p = DO_UPCAST(PCIEPort, br, br); PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
int rc; int rc;
@ -118,9 +118,9 @@ PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
if (!d) { if (!d) {
return NULL; return NULL;
} }
br = DO_UPCAST(PCIBridge, dev, d); br = PCI_BRIDGE(d);
qdev = &br->dev.qdev; qdev = DEVICE(d);
pci_bridge_map_irq(br, bus_name, map_irq); pci_bridge_map_irq(br, bus_name, map_irq);
qdev_prop_set_uint8(qdev, "port", port); qdev_prop_set_uint8(qdev, "port", port);
qdev_init_nofail(qdev); qdev_init_nofail(qdev);
@ -134,17 +134,18 @@ static const VMStateDescription vmstate_xio3130_upstream = {
.minimum_version_id = 1, .minimum_version_id = 1,
.minimum_version_id_old = 1, .minimum_version_id_old = 1,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_PCIE_DEVICE(br.dev, PCIEPort), VMSTATE_PCIE_DEVICE(br.parent_obj, PCIEPort),
VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log, VMSTATE_STRUCT(br.parent_obj.exp.aer_log, PCIEPort, 0,
PCIEAERLog), vmstate_pcie_aer_log, PCIEAERLog),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
static Property xio3130_upstream_properties[] = { static Property xio3130_upstream_properties[] = {
DEFINE_PROP_UINT8("port", PCIEPort, port, 0), DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log_max, DEFINE_PROP_UINT16("aer_log_max", PCIEPort,
PCIE_AER_LOG_MAX_DEFAULT), br.parent_obj.exp.aer_log.log_max,
PCIE_AER_LOG_MAX_DEFAULT),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };
@ -170,7 +171,7 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
static const TypeInfo xio3130_upstream_info = { static const TypeInfo xio3130_upstream_info = {
.name = "x3130-upstream", .name = "x3130-upstream",
.parent = TYPE_PCI_DEVICE, .parent = TYPE_PCI_BRIDGE,
.instance_size = sizeof(PCIEPort), .instance_size = sizeof(PCIEPort),
.class_init = xio3130_upstream_class_init, .class_init = xio3130_upstream_class_init,
}; };

7
hw/pci-host/apb.c
View File

@ -423,7 +423,7 @@ PCIBus *pci_apb_init(hwaddr special_base,
/* APB secondary busses */ /* APB secondary busses */
pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
"pbm-bridge"); "pbm-bridge");
br = DO_UPCAST(PCIBridge, dev, pci_dev); br = PCI_BRIDGE(pci_dev);
pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1", pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
pci_apb_map_irq); pci_apb_map_irq);
qdev_init_nofail(&pci_dev->qdev); qdev_init_nofail(&pci_dev->qdev);
@ -431,7 +431,7 @@ PCIBus *pci_apb_init(hwaddr special_base,
pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
"pbm-bridge"); "pbm-bridge");
br = DO_UPCAST(PCIBridge, dev, pci_dev); br = PCI_BRIDGE(pci_dev);
pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2", pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
pci_apb_map_irq); pci_apb_map_irq);
qdev_init_nofail(&pci_dev->qdev); qdev_init_nofail(&pci_dev->qdev);
@ -566,8 +566,7 @@ static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
static const TypeInfo pbm_pci_bridge_info = { static const TypeInfo pbm_pci_bridge_info = {
.name = "pbm-bridge", .name = "pbm-bridge",
.parent = TYPE_PCI_DEVICE, .parent = TYPE_PCI_BRIDGE,
.instance_size = sizeof(PCIBridge),
.class_init = pbm_pci_bridge_class_init, .class_init = pbm_pci_bridge_class_init,
}; };

2
hw/pci/pci.c
View File

@ -397,7 +397,7 @@ static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
pci_update_mappings(s); pci_update_mappings(s);
if (pc->is_bridge) { if (pc->is_bridge) {
PCIBridge *b = container_of(s, PCIBridge, dev); PCIBridge *b = PCI_BRIDGE(s);
pci_bridge_update_mappings(b); pci_bridge_update_mappings(b);
} }

40
hw/pci/pci_bridge.c
View File

@ -141,8 +141,9 @@ static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,
MemoryRegion *parent_space, MemoryRegion *parent_space,
bool enabled) bool enabled)
{ {
pcibus_t base = pci_bridge_get_base(&bridge->dev, type); PCIDevice *bridge_dev = PCI_DEVICE(bridge);
pcibus_t limit = pci_bridge_get_limit(&bridge->dev, type); pcibus_t base = pci_bridge_get_base(bridge_dev, type);
pcibus_t limit = pci_bridge_get_limit(bridge_dev, type);
/* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly. /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
* Apparently no way to do this with existing memory APIs. */ * Apparently no way to do this with existing memory APIs. */
pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0; pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;
@ -154,7 +155,8 @@ static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,
static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent, static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,
MemoryRegion *alias_vga) MemoryRegion *alias_vga)
{ {
uint16_t brctl = pci_get_word(br->dev.config + PCI_BRIDGE_CONTROL); PCIDevice *pd = PCI_DEVICE(br);
uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL);
memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br), memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br),
"pci_bridge_vga_io_lo", &br->address_space_io, "pci_bridge_vga_io_lo", &br->address_space_io,
@ -167,7 +169,7 @@ static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,
QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE); QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);
if (brctl & PCI_BRIDGE_CTL_VGA) { if (brctl & PCI_BRIDGE_CTL_VGA) {
pci_register_vga(&br->dev, &alias_vga[QEMU_PCI_VGA_MEM], pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM],
&alias_vga[QEMU_PCI_VGA_IO_LO], &alias_vga[QEMU_PCI_VGA_IO_LO],
&alias_vga[QEMU_PCI_VGA_IO_HI]); &alias_vga[QEMU_PCI_VGA_IO_HI]);
} }
@ -175,9 +177,10 @@ static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,
static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br) static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br)
{ {
PCIBus *parent = br->dev.bus; PCIDevice *pd = PCI_DEVICE(br);
PCIBus *parent = pd->bus;
PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1); PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1);
uint16_t cmd = pci_get_word(br->dev.config + PCI_COMMAND); uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND);
pci_bridge_init_alias(br, &w->alias_pref_mem, pci_bridge_init_alias(br, &w->alias_pref_mem,
PCI_BASE_ADDRESS_MEM_PREFETCH, PCI_BASE_ADDRESS_MEM_PREFETCH,
@ -205,12 +208,13 @@ static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br)
static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w) static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w)
{ {
PCIBus *parent = br->dev.bus; PCIDevice *pd = PCI_DEVICE(br);
PCIBus *parent = pd->bus;
memory_region_del_subregion(parent->address_space_io, &w->alias_io); memory_region_del_subregion(parent->address_space_io, &w->alias_io);
memory_region_del_subregion(parent->address_space_mem, &w->alias_mem); memory_region_del_subregion(parent->address_space_mem, &w->alias_mem);
memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem); memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem);
pci_unregister_vga(&br->dev); pci_unregister_vga(pd);
} }
static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w) static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w)
@ -241,7 +245,7 @@ void pci_bridge_update_mappings(PCIBridge *br)
void pci_bridge_write_config(PCIDevice *d, void pci_bridge_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len) uint32_t address, uint32_t val, int len)
{ {
PCIBridge *s = container_of(d, PCIBridge, dev); PCIBridge *s = PCI_BRIDGE(d);
uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
uint16_t newctl; uint16_t newctl;
@ -331,7 +335,7 @@ void pci_bridge_reset(DeviceState *qdev)
int pci_bridge_initfn(PCIDevice *dev, const char *typename) int pci_bridge_initfn(PCIDevice *dev, const char *typename)
{ {
PCIBus *parent = dev->bus; PCIBus *parent = dev->bus;
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev); PCIBridge *br = PCI_BRIDGE(dev);
PCIBus *sec_bus = &br->sec_bus; PCIBus *sec_bus = &br->sec_bus;
pci_word_test_and_set_mask(dev->config + PCI_STATUS, pci_word_test_and_set_mask(dev->config + PCI_STATUS,
@ -379,7 +383,7 @@ int pci_bridge_initfn(PCIDevice *dev, const char *typename)
/* default qdev clean up function for PCI-to-PCI bridge */ /* default qdev clean up function for PCI-to-PCI bridge */
void pci_bridge_exitfn(PCIDevice *pci_dev) void pci_bridge_exitfn(PCIDevice *pci_dev)
{ {
PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev); PCIBridge *s = PCI_BRIDGE(pci_dev);
assert(QLIST_EMPTY(&s->sec_bus.child)); assert(QLIST_EMPTY(&s->sec_bus.child));
QLIST_REMOVE(&s->sec_bus, sibling); QLIST_REMOVE(&s->sec_bus, sibling);
pci_bridge_region_del(s, s->windows); pci_bridge_region_del(s, s->windows);
@ -400,3 +404,17 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
br->map_irq = map_irq; br->map_irq = map_irq;
br->bus_name = bus_name; br->bus_name = bus_name;
} }
static const TypeInfo pci_bridge_type_info = {
.name = TYPE_PCI_BRIDGE,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIBridge),
.abstract = true,
};
static void pci_bridge_register_types(void)
{
type_register_static(&pci_bridge_type_info);
}
type_init(pci_bridge_register_types)

2
hw/pci/pcie.c
View File

@ -305,7 +305,7 @@ void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
dev->exp.hpev_notified = false; dev->exp.hpev_notified = false;
pci_bus_hotplug(pci_bridge_get_sec_bus(DO_UPCAST(PCIBridge, dev, dev)), pci_bus_hotplug(pci_bridge_get_sec_bus(PCI_BRIDGE(dev)),
pcie_cap_slot_hotplug, &dev->qdev); pcie_cap_slot_hotplug, &dev->qdev);
} }

7
include/hw/pci/pci_bus.h
View File

@ -53,8 +53,13 @@ struct PCIBridgeWindows {
MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS]; MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS];
}; };
#define TYPE_PCI_BRIDGE "base-pci-bridge"
#define PCI_BRIDGE(obj) OBJECT_CHECK(PCIBridge, (obj), TYPE_PCI_BRIDGE)
struct PCIBridge { struct PCIBridge {
PCIDevice dev; /*< private >*/
PCIDevice parent_obj;
/*< public >*/
/* private member */ /* private member */
PCIBus sec_bus; PCIBus sec_bus;