4a8e490cbc
target-openrisc: remove conflicting definitions from cpu.h
...
On an ARM host, the registers definitions from cpu.h clash
with /usr/include/sys/ucontext.h. As there are unused, just remove
them.
Cc: Jia Liu <proljc@gmail.com>
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
(cherry picked from commit 44e04d3b94
2012-12-03 13:23:11 -06:00
d962783e98
target-or32: Add linux user support
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Add QEMU OpenRISC linux user support.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:13:05 +00:00
4dd044c6ba
target-or32: Add system instructions
...
Add OpenRISC system instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:13:03 +00:00
99f575edcc
target-or32: Add timer support
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Add OpenRISC timer support.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:13:02 +00:00
dd29c7fb01
target-or32: Add PIC support
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Add OpenRISC Programmable Interrupt Controller support.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:13:01 +00:00
b6a71ef7e0
target-or32: Add interrupt support
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Add OpenRISC interrupt support.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:12:57 +00:00
726fe04572
target-or32: Add MMU support
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Add OpenRISC MMU support.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:12:56 +00:00
e67db06e9f
target-or32: Add target stubs and QOM cpu
...
Add OpenRISC target stubs, QOM cpu and basic machine.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:12:55 +00:00
Aurelien Jarno