aurel32
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59d9413094
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target-mips: CP0 Random register improvements
- Use a LFSR to generate the random value
- Make sure to not return the same value twice
Based on a patch by Hervé Poussineau.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6233 c046a42c-6fe2-441c-8c8c-71466251a162
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2009-01-08 18:48:12 +00:00 |
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aurel32
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75973fa1ee
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MIPS: remove empty cpu_mips_irqctrl_init()
cpu_mips_irqctrl_init() function in hw/mips_timer.c is empty.
Attached patch removes it, and its callers.
(Hervé Poussineau)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5214 c046a42c-6fe2-441c-8c8c-71466251a162
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2008-09-14 16:38:57 +00:00 |
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pbrook
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2e70f6efa8
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Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
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2008-06-29 01:03:05 +00:00 |
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aurel32
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ea86e4e600
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Optimize MIPS timer read/write functions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4190 c046a42c-6fe2-441c-8c8c-71466251a162
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2008-04-11 04:55:31 +00:00 |
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pbrook
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87ecb68bdf
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Break up vl.h.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3674 c046a42c-6fe2-441c-8c8c-71466251a162
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2007-11-17 17:14:51 +00:00 |
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ths
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42532189df
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Timer start/stop implementation, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3237 c046a42c-6fe2-441c-8c8c-71466251a162
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2007-09-25 16:53:15 +00:00 |
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ths
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ead9360e2f
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Partial support for 34K multithreading, not functional yet.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3156 c046a42c-6fe2-441c-8c8c-71466251a162
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2007-09-06 00:18:15 +00:00 |
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ths
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fcb4a419f5
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Choose number of TLBs at runtime, by Herve Poussineau.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2693 c046a42c-6fe2-441c-8c8c-71466251a162
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2007-04-17 15:26:47 +00:00 |
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pbrook
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d537cf6c86
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Unify IRQ handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162
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2007-04-07 18:14:41 +00:00 |
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ths
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3529b538ce
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Fix disabling of the Cause register for R2.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2612 c046a42c-6fe2-441c-8c8c-71466251a162
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2007-04-05 23:17:40 +00:00 |
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ths
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39d51eb8bc
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Fix BD flag handling, cause register contents, implement some more bits
for R2 interrupt handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2493 c046a42c-6fe2-441c-8c8c-71466251a162
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2007-03-18 12:43:40 +00:00 |
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ths
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4de9b249d3
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Reworking MIPS interrupt handling, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2350 c046a42c-6fe2-441c-8c8c-71466251a162
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2007-01-24 01:47:51 +00:00 |
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ths
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e16fe40c87
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Move the MIPS CPU timer in a seperate file, by Alec Voropay.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2225 c046a42c-6fe2-441c-8c8c-71466251a162
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2006-12-06 21:38:37 +00:00 |