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Eric Johnson 849c865155 target-mips: allow microMIPS SWP and SDP to have RD equal to BASE 
The microMIPS SWP and SDP instructions do not modify GPRs.  So their
behavior is well defined when RD equals BASE.  The MIPS Architecture
Verification Programs (AVPs) check that they work as expected.  This
is required for AVPs to pass.

Signed-off-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
(cherry picked from commit 36c6711bbe)

Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
 		2012-08-28 14:38:44 -05:00
..
TODO Replace Qemu by QEMU in internal documentation 2012-04-07 13:58:25 +00:00
cpu-qom.h target-mips: QOM'ify CPU 2012-04-30 11:32:13 +02:00
cpu.c target-mips: Start QOM'ifying CPU init 2012-04-30 11:32:13 +02:00
cpu.h target-mips: Remove commented-out function declaration 2012-05-12 14:17:52 +02:00
helper.c target-mips: Don't overuse CPUState 2012-03-14 22:20:25 +01:00
helper.h target-mips: Add compiler attribute to some functions which don't return 2012-03-24 13:02:43 +00:00
machine.c target-mips: Don't overuse CPUState 2012-03-14 22:20:25 +01:00
mips-defs.h
…
op_helper.c target-mips: Fix some helper functions (VR54xx multiplication) 2012-08-28 01:50:02 -05:00
translate.c target-mips: allow microMIPS SWP and SDP to have RD equal to BASE 2012-08-28 14:38:44 -05:00
translate_init.c mips: Default to using one VPE and one TC. 2011-09-06 11:09:39 +02:00