850 lines
24 KiB
C
850 lines
24 KiB
C
/*
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* ARM translation
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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/* internal defines */
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typedef struct DisasContext {
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uint8_t *pc;
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int is_jmp;
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struct TranslationBlock *tb;
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} DisasContext;
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#define DISAS_JUMP_NEXT 4
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/* XXX: move that elsewhere */
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
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extern FILE *logfile;
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extern int loglevel;
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enum {
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#define DEF(s, n, copy_size) INDEX_op_ ## s,
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#include "opc.h"
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#undef DEF
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NB_OPS,
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};
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#include "gen-op.h"
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static GenOpFunc2 *gen_test_cc[14] = {
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gen_op_test_eq,
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gen_op_test_ne,
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gen_op_test_cs,
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gen_op_test_cc,
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gen_op_test_mi,
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gen_op_test_pl,
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gen_op_test_vs,
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gen_op_test_vc,
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gen_op_test_hi,
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gen_op_test_ls,
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gen_op_test_ge,
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gen_op_test_lt,
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gen_op_test_gt,
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gen_op_test_le,
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};
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const uint8_t table_logic_cc[16] = {
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1, /* and */
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1, /* xor */
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0, /* sub */
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0, /* rsb */
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0, /* add */
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0, /* adc */
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0, /* sbc */
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0, /* rsc */
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1, /* andl */
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1, /* xorl */
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0, /* cmp */
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0, /* cmn */
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1, /* orr */
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1, /* mov */
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1, /* bic */
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1, /* mvn */
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};
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static GenOpFunc1 *gen_shift_T1_im[4] = {
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gen_op_shll_T1_im,
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gen_op_shrl_T1_im,
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gen_op_sarl_T1_im,
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gen_op_rorl_T1_im,
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};
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static GenOpFunc1 *gen_shift_T2_im[4] = {
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gen_op_shll_T2_im,
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gen_op_shrl_T2_im,
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gen_op_sarl_T2_im,
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gen_op_rorl_T2_im,
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};
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static GenOpFunc1 *gen_shift_T1_im_cc[4] = {
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gen_op_shll_T1_im_cc,
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gen_op_shrl_T1_im_cc,
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gen_op_sarl_T1_im_cc,
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gen_op_rorl_T1_im_cc,
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};
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static GenOpFunc *gen_shift_T1_T0[4] = {
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gen_op_shll_T1_T0,
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gen_op_shrl_T1_T0,
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gen_op_sarl_T1_T0,
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gen_op_rorl_T1_T0,
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};
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static GenOpFunc *gen_shift_T1_T0_cc[4] = {
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gen_op_shll_T1_T0_cc,
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gen_op_shrl_T1_T0_cc,
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gen_op_sarl_T1_T0_cc,
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gen_op_rorl_T1_T0_cc,
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};
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static GenOpFunc *gen_op_movl_TN_reg[3][16] = {
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{
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gen_op_movl_T0_r0,
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gen_op_movl_T0_r1,
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gen_op_movl_T0_r2,
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gen_op_movl_T0_r3,
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gen_op_movl_T0_r4,
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gen_op_movl_T0_r5,
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gen_op_movl_T0_r6,
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gen_op_movl_T0_r7,
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gen_op_movl_T0_r8,
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gen_op_movl_T0_r9,
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gen_op_movl_T0_r10,
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gen_op_movl_T0_r11,
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gen_op_movl_T0_r12,
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gen_op_movl_T0_r13,
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gen_op_movl_T0_r14,
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gen_op_movl_T0_r15,
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},
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{
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gen_op_movl_T1_r0,
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gen_op_movl_T1_r1,
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gen_op_movl_T1_r2,
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gen_op_movl_T1_r3,
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gen_op_movl_T1_r4,
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gen_op_movl_T1_r5,
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gen_op_movl_T1_r6,
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gen_op_movl_T1_r7,
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gen_op_movl_T1_r8,
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gen_op_movl_T1_r9,
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gen_op_movl_T1_r10,
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gen_op_movl_T1_r11,
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gen_op_movl_T1_r12,
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gen_op_movl_T1_r13,
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gen_op_movl_T1_r14,
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gen_op_movl_T1_r15,
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},
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{
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gen_op_movl_T2_r0,
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gen_op_movl_T2_r1,
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gen_op_movl_T2_r2,
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gen_op_movl_T2_r3,
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gen_op_movl_T2_r4,
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gen_op_movl_T2_r5,
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gen_op_movl_T2_r6,
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gen_op_movl_T2_r7,
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gen_op_movl_T2_r8,
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gen_op_movl_T2_r9,
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gen_op_movl_T2_r10,
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gen_op_movl_T2_r11,
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gen_op_movl_T2_r12,
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gen_op_movl_T2_r13,
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gen_op_movl_T2_r14,
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gen_op_movl_T2_r15,
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},
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};
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static GenOpFunc *gen_op_movl_reg_TN[2][16] = {
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{
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gen_op_movl_r0_T0,
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gen_op_movl_r1_T0,
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gen_op_movl_r2_T0,
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gen_op_movl_r3_T0,
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gen_op_movl_r4_T0,
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gen_op_movl_r5_T0,
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gen_op_movl_r6_T0,
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gen_op_movl_r7_T0,
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gen_op_movl_r8_T0,
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gen_op_movl_r9_T0,
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gen_op_movl_r10_T0,
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gen_op_movl_r11_T0,
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gen_op_movl_r12_T0,
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gen_op_movl_r13_T0,
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gen_op_movl_r14_T0,
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gen_op_movl_r15_T0,
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},
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{
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gen_op_movl_r0_T1,
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gen_op_movl_r1_T1,
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gen_op_movl_r2_T1,
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gen_op_movl_r3_T1,
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gen_op_movl_r4_T1,
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gen_op_movl_r5_T1,
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gen_op_movl_r6_T1,
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gen_op_movl_r7_T1,
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gen_op_movl_r8_T1,
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gen_op_movl_r9_T1,
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gen_op_movl_r10_T1,
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gen_op_movl_r11_T1,
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gen_op_movl_r12_T1,
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gen_op_movl_r13_T1,
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gen_op_movl_r14_T1,
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gen_op_movl_r15_T1,
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},
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};
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static GenOpFunc1 *gen_op_movl_TN_im[3] = {
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gen_op_movl_T0_im,
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gen_op_movl_T1_im,
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gen_op_movl_T2_im,
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};
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static inline void gen_movl_TN_reg(DisasContext *s, int reg, int t)
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{
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int val;
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if (reg == 15) {
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/* normaly, since we updated PC, we need only to add 4 */
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val = (long)s->pc + 4;
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gen_op_movl_TN_im[t](val);
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} else {
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gen_op_movl_TN_reg[t][reg]();
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}
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}
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static inline void gen_movl_T0_reg(DisasContext *s, int reg)
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{
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gen_movl_TN_reg(s, reg, 0);
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}
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static inline void gen_movl_T1_reg(DisasContext *s, int reg)
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{
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gen_movl_TN_reg(s, reg, 1);
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}
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static inline void gen_movl_T2_reg(DisasContext *s, int reg)
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{
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gen_movl_TN_reg(s, reg, 2);
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}
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static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t)
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{
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gen_op_movl_reg_TN[t][reg]();
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if (reg == 15) {
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s->is_jmp = DISAS_JUMP;
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}
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}
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static inline void gen_movl_reg_T0(DisasContext *s, int reg)
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{
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gen_movl_reg_TN(s, reg, 0);
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}
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static inline void gen_movl_reg_T1(DisasContext *s, int reg)
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{
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gen_movl_reg_TN(s, reg, 1);
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}
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static inline void gen_add_data_offset(DisasContext *s, unsigned int insn)
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{
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int val, rm, shift;
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if (!(insn & (1 << 25))) {
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/* immediate */
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val = insn & 0xfff;
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if (!(insn & (1 << 23)))
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val = -val;
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if (val != 0)
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gen_op_addl_T1_im(val);
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} else {
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/* shift/register */
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rm = (insn) & 0xf;
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shift = (insn >> 7) & 0x1f;
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gen_movl_T2_reg(s, rm);
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if (shift != 0) {
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gen_shift_T2_im[(insn >> 5) & 3](shift);
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}
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if (!(insn & (1 << 23)))
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gen_op_subl_T1_T2();
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else
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gen_op_addl_T1_T2();
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}
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}
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static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn)
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{
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int val, rm;
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if (insn & (1 << 22)) {
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/* immediate */
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val = (insn & 0xf) | ((insn >> 4) & 0xf0);
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if (!(insn & (1 << 23)))
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val = -val;
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if (val != 0)
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gen_op_addl_T1_im(val);
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} else {
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/* register */
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rm = (insn) & 0xf;
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gen_movl_T2_reg(s, rm);
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if (!(insn & (1 << 23)))
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gen_op_subl_T1_T2();
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else
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gen_op_addl_T1_T2();
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}
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}
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static void disas_arm_insn(DisasContext *s)
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{
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unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
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insn = ldl(s->pc);
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s->pc += 4;
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cond = insn >> 28;
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if (cond == 0xf)
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goto illegal_op;
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if (cond != 0xe) {
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/* if not always execute, we generate a conditional jump to
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next instruction */
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gen_test_cc[cond ^ 1]((long)s->tb, (long)s->pc);
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s->is_jmp = DISAS_JUMP_NEXT;
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}
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if (((insn & 0x0e000000) == 0 &&
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(insn & 0x00000090) != 0x90) ||
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((insn & 0x0e000000) == (1 << 25))) {
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int set_cc, logic_cc, shiftop;
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op1 = (insn >> 21) & 0xf;
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set_cc = (insn >> 20) & 1;
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logic_cc = table_logic_cc[op1] & set_cc;
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/* data processing instruction */
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if (insn & (1 << 25)) {
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/* immediate operand */
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val = insn & 0xff;
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shift = ((insn >> 8) & 0xf) * 2;
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if (shift)
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val = (val >> shift) | (val << (32 - shift));
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gen_op_movl_T1_im(val);
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/* XXX: is CF modified ? */
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} else {
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/* register */
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rm = (insn) & 0xf;
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gen_movl_T1_reg(s, rm);
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shiftop = (insn >> 5) & 3;
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if (!(insn & (1 << 4))) {
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shift = (insn >> 7) & 0x1f;
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if (shift != 0) {
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if (logic_cc) {
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gen_shift_T1_im_cc[shiftop](shift);
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} else {
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gen_shift_T1_im[shiftop](shift);
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}
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}
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} else {
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rs = (insn >> 8) & 0xf;
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gen_movl_T0_reg(s, rs);
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if (logic_cc) {
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gen_shift_T1_T0_cc[shiftop]();
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} else {
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gen_shift_T1_T0[shiftop]();
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}
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}
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}
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if (op1 != 0x0f && op1 != 0x0d) {
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rn = (insn >> 16) & 0xf;
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gen_movl_T0_reg(s, rn);
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}
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rd = (insn >> 12) & 0xf;
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switch(op1) {
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case 0x00:
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gen_op_andl_T0_T1();
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gen_movl_reg_T0(s, rd);
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if (logic_cc)
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gen_op_logic_T0_cc();
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break;
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case 0x01:
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gen_op_xorl_T0_T1();
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gen_movl_reg_T0(s, rd);
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if (logic_cc)
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gen_op_logic_T0_cc();
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break;
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case 0x02:
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if (set_cc)
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gen_op_subl_T0_T1_cc();
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else
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gen_op_subl_T0_T1();
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gen_movl_reg_T0(s, rd);
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break;
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case 0x03:
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if (set_cc)
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gen_op_rsbl_T0_T1_cc();
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else
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gen_op_rsbl_T0_T1();
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gen_movl_reg_T0(s, rd);
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break;
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case 0x04:
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if (set_cc)
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gen_op_addl_T0_T1_cc();
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else
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gen_op_addl_T0_T1();
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gen_movl_reg_T0(s, rd);
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break;
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case 0x05:
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if (set_cc)
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gen_op_adcl_T0_T1_cc();
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else
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gen_op_adcl_T0_T1();
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gen_movl_reg_T0(s, rd);
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break;
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case 0x06:
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if (set_cc)
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gen_op_sbcl_T0_T1_cc();
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else
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gen_op_sbcl_T0_T1();
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gen_movl_reg_T0(s, rd);
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break;
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case 0x07:
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if (set_cc)
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gen_op_rscl_T0_T1_cc();
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else
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gen_op_rscl_T0_T1();
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gen_movl_reg_T0(s, rd);
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break;
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case 0x08:
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if (set_cc) {
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gen_op_andl_T0_T1();
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gen_op_logic_T0_cc();
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}
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break;
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case 0x09:
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if (set_cc) {
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gen_op_xorl_T0_T1();
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gen_op_logic_T0_cc();
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}
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break;
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case 0x0a:
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if (set_cc) {
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gen_op_subl_T0_T1_cc();
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}
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break;
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case 0x0b:
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if (set_cc) {
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gen_op_addl_T0_T1_cc();
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}
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break;
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case 0x0c:
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gen_op_orl_T0_T1();
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gen_movl_reg_T0(s, rd);
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if (logic_cc)
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gen_op_logic_T0_cc();
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break;
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case 0x0d:
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gen_movl_reg_T1(s, rd);
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if (logic_cc)
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gen_op_logic_T1_cc();
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break;
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case 0x0e:
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gen_op_bicl_T0_T1();
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gen_movl_reg_T0(s, rd);
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if (logic_cc)
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gen_op_logic_T0_cc();
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break;
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default:
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case 0x0f:
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gen_op_notl_T1();
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gen_movl_reg_T1(s, rd);
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if (logic_cc)
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gen_op_logic_T1_cc();
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break;
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}
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} else {
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/* other instructions */
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op1 = (insn >> 24) & 0xf;
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switch(op1) {
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case 0x0:
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case 0x1:
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sh = (insn >> 5) & 3;
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if (sh == 0) {
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if (op1 == 0x0) {
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|
rd = (insn >> 16) & 0xf;
|
|
rn = (insn >> 12) & 0xf;
|
|
rs = (insn >> 8) & 0xf;
|
|
rm = (insn) & 0xf;
|
|
if (!(insn & (1 << 23))) {
|
|
/* 32 bit mul */
|
|
gen_movl_T0_reg(s, rs);
|
|
gen_movl_T1_reg(s, rm);
|
|
gen_op_mul_T0_T1();
|
|
if (insn & (1 << 21)) {
|
|
gen_movl_T1_reg(s, rn);
|
|
gen_op_addl_T0_T1();
|
|
}
|
|
if (insn & (1 << 20))
|
|
gen_op_logic_T0_cc();
|
|
gen_movl_reg_T0(s, rd);
|
|
} else {
|
|
/* 64 bit mul */
|
|
gen_movl_T0_reg(s, rs);
|
|
gen_movl_T1_reg(s, rm);
|
|
if (insn & (1 << 22))
|
|
gen_op_imull_T0_T1();
|
|
else
|
|
gen_op_mull_T0_T1();
|
|
if (insn & (1 << 21))
|
|
gen_op_addq_T0_T1(rn, rd);
|
|
if (insn & (1 << 20))
|
|
gen_op_logicq_cc();
|
|
gen_movl_reg_T0(s, rn);
|
|
gen_movl_reg_T1(s, rd);
|
|
}
|
|
} else {
|
|
/* SWP instruction */
|
|
rn = (insn >> 16) & 0xf;
|
|
rd = (insn >> 12) & 0xf;
|
|
rm = (insn) & 0xf;
|
|
|
|
gen_movl_T0_reg(s, rm);
|
|
gen_movl_T1_reg(s, rn);
|
|
if (insn & (1 << 22)) {
|
|
gen_op_swpb_T0_T1();
|
|
} else {
|
|
gen_op_swpl_T0_T1();
|
|
}
|
|
gen_movl_reg_T0(s, rd);
|
|
}
|
|
} else {
|
|
/* load/store half word */
|
|
rn = (insn >> 16) & 0xf;
|
|
rd = (insn >> 12) & 0xf;
|
|
gen_movl_T1_reg(s, rn);
|
|
if (insn & (1 << 24))
|
|
gen_add_datah_offset(s, insn);
|
|
if (insn & (1 << 20)) {
|
|
/* load */
|
|
switch(sh) {
|
|
case 1:
|
|
gen_op_lduw_T0_T1();
|
|
break;
|
|
case 2:
|
|
gen_op_ldsb_T0_T1();
|
|
break;
|
|
default:
|
|
case 3:
|
|
gen_op_ldsw_T0_T1();
|
|
break;
|
|
}
|
|
gen_movl_reg_T0(s, rd);
|
|
} else {
|
|
/* store */
|
|
gen_movl_T0_reg(s, rd);
|
|
gen_op_stw_T0_T1();
|
|
}
|
|
if (!(insn & (1 << 24))) {
|
|
gen_add_datah_offset(s, insn);
|
|
gen_movl_reg_T1(s, rn);
|
|
} else if (insn & (1 << 21)) {
|
|
gen_movl_reg_T1(s, rn);
|
|
}
|
|
}
|
|
break;
|
|
case 0x4:
|
|
case 0x5:
|
|
case 0x6:
|
|
case 0x7:
|
|
/* load/store byte/word */
|
|
rn = (insn >> 16) & 0xf;
|
|
rd = (insn >> 12) & 0xf;
|
|
gen_movl_T1_reg(s, rn);
|
|
if (insn & (1 << 24))
|
|
gen_add_data_offset(s, insn);
|
|
if (insn & (1 << 20)) {
|
|
/* load */
|
|
if (insn & (1 << 22))
|
|
gen_op_ldub_T0_T1();
|
|
else
|
|
gen_op_ldl_T0_T1();
|
|
gen_movl_reg_T0(s, rd);
|
|
} else {
|
|
/* store */
|
|
gen_movl_T0_reg(s, rd);
|
|
if (insn & (1 << 22))
|
|
gen_op_stb_T0_T1();
|
|
else
|
|
gen_op_stl_T0_T1();
|
|
}
|
|
if (!(insn & (1 << 24))) {
|
|
gen_add_data_offset(s, insn);
|
|
gen_movl_reg_T1(s, rn);
|
|
} else if (insn & (1 << 21))
|
|
gen_movl_reg_T1(s, rn); {
|
|
}
|
|
break;
|
|
case 0x08:
|
|
case 0x09:
|
|
{
|
|
int j, n;
|
|
/* load/store multiple words */
|
|
/* XXX: store correct base if write back */
|
|
if (insn & (1 << 22))
|
|
goto illegal_op; /* only usable in supervisor mode */
|
|
rn = (insn >> 16) & 0xf;
|
|
gen_movl_T1_reg(s, rn);
|
|
|
|
/* compute total size */
|
|
n = 0;
|
|
for(i=0;i<16;i++) {
|
|
if (insn & (1 << i))
|
|
n++;
|
|
}
|
|
/* XXX: test invalid n == 0 case ? */
|
|
if (insn & (1 << 23)) {
|
|
if (insn & (1 << 24)) {
|
|
/* pre increment */
|
|
gen_op_addl_T1_im(4);
|
|
} else {
|
|
/* post increment */
|
|
}
|
|
} else {
|
|
if (insn & (1 << 24)) {
|
|
/* pre decrement */
|
|
gen_op_addl_T1_im(-(n * 4));
|
|
} else {
|
|
/* post decrement */
|
|
if (n != 1)
|
|
gen_op_addl_T1_im(-((n - 1) * 4));
|
|
}
|
|
}
|
|
j = 0;
|
|
for(i=0;i<16;i++) {
|
|
if (insn & (1 << i)) {
|
|
if (insn & (1 << 20)) {
|
|
/* load */
|
|
gen_op_ldl_T0_T1();
|
|
gen_movl_reg_T0(s, i);
|
|
} else {
|
|
/* store */
|
|
if (i == 15) {
|
|
/* special case: r15 = PC + 12 */
|
|
val = (long)s->pc + 8;
|
|
gen_op_movl_TN_im[0](val);
|
|
} else {
|
|
gen_movl_T0_reg(s, i);
|
|
}
|
|
gen_op_stl_T0_T1();
|
|
}
|
|
j++;
|
|
/* no need to add after the last transfer */
|
|
if (j != n)
|
|
gen_op_addl_T1_im(4);
|
|
}
|
|
}
|
|
if (insn & (1 << 21)) {
|
|
/* write back */
|
|
if (insn & (1 << 23)) {
|
|
if (insn & (1 << 24)) {
|
|
/* pre increment */
|
|
} else {
|
|
/* post increment */
|
|
gen_op_addl_T1_im(4);
|
|
}
|
|
} else {
|
|
if (insn & (1 << 24)) {
|
|
/* pre decrement */
|
|
if (n != 1)
|
|
gen_op_addl_T1_im(-((n - 1) * 4));
|
|
} else {
|
|
/* post decrement */
|
|
gen_op_addl_T1_im(-(n * 4));
|
|
}
|
|
}
|
|
gen_movl_reg_T1(s, rn);
|
|
}
|
|
}
|
|
break;
|
|
case 0xa:
|
|
case 0xb:
|
|
{
|
|
int offset;
|
|
|
|
/* branch (and link) */
|
|
val = (int)s->pc;
|
|
if (insn & (1 << 24)) {
|
|
gen_op_movl_T0_im(val);
|
|
gen_op_movl_reg_TN[0][14]();
|
|
}
|
|
offset = (((int)insn << 8) >> 8);
|
|
val += (offset << 2) + 4;
|
|
gen_op_jmp((long)s->tb, val);
|
|
s->is_jmp = DISAS_TB_JUMP;
|
|
}
|
|
break;
|
|
case 0xf:
|
|
/* swi */
|
|
gen_op_movl_T0_im((long)s->pc);
|
|
gen_op_movl_reg_TN[0][15]();
|
|
gen_op_swi();
|
|
s->is_jmp = DISAS_JUMP;
|
|
break;
|
|
default:
|
|
illegal_op:
|
|
gen_op_movl_T0_im((long)s->pc - 4);
|
|
gen_op_movl_reg_TN[0][15]();
|
|
gen_op_undef_insn();
|
|
s->is_jmp = DISAS_JUMP;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
|
|
basic block 'tb'. If search_pc is TRUE, also generate PC
|
|
information for each intermediate instruction. */
|
|
static inline int gen_intermediate_code_internal(CPUState *env,
|
|
TranslationBlock *tb,
|
|
int search_pc)
|
|
{
|
|
DisasContext dc1, *dc = &dc1;
|
|
uint16_t *gen_opc_end;
|
|
int j, lj;
|
|
uint8_t *pc_start;
|
|
|
|
/* generate intermediate code */
|
|
pc_start = (uint8_t *)tb->pc;
|
|
|
|
dc->tb = tb;
|
|
|
|
gen_opc_ptr = gen_opc_buf;
|
|
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
|
|
gen_opparam_ptr = gen_opparam_buf;
|
|
|
|
dc->is_jmp = DISAS_NEXT;
|
|
dc->pc = pc_start;
|
|
lj = -1;
|
|
do {
|
|
if (search_pc) {
|
|
j = gen_opc_ptr - gen_opc_buf;
|
|
if (lj < j) {
|
|
lj++;
|
|
while (lj < j)
|
|
gen_opc_instr_start[lj++] = 0;
|
|
}
|
|
gen_opc_pc[lj] = (uint32_t)dc->pc;
|
|
gen_opc_instr_start[lj] = 1;
|
|
}
|
|
disas_arm_insn(dc);
|
|
} while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
|
|
(dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
|
|
switch(dc->is_jmp) {
|
|
case DISAS_JUMP_NEXT:
|
|
case DISAS_NEXT:
|
|
gen_op_jmp((long)dc->tb, (long)dc->pc);
|
|
break;
|
|
default:
|
|
case DISAS_JUMP:
|
|
/* indicate that the hash table must be used to find the next TB */
|
|
gen_op_movl_T0_0();
|
|
gen_op_exit_tb();
|
|
break;
|
|
case DISAS_TB_JUMP:
|
|
/* nothing more to generate */
|
|
break;
|
|
}
|
|
*gen_opc_ptr = INDEX_op_end;
|
|
|
|
#ifdef DEBUG_DISAS
|
|
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
fprintf(logfile, "----------------\n");
|
|
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
|
disas(logfile, pc_start, dc->pc - pc_start, 0, 0);
|
|
fprintf(logfile, "\n");
|
|
if (loglevel & (CPU_LOG_TB_OP)) {
|
|
fprintf(logfile, "OP:\n");
|
|
dump_ops(gen_opc_buf, gen_opparam_buf);
|
|
fprintf(logfile, "\n");
|
|
}
|
|
}
|
|
#endif
|
|
if (!search_pc)
|
|
tb->size = dc->pc - pc_start;
|
|
return 0;
|
|
}
|
|
|
|
int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
|
|
{
|
|
return gen_intermediate_code_internal(env, tb, 0);
|
|
}
|
|
|
|
int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
|
|
{
|
|
return gen_intermediate_code_internal(env, tb, 1);
|
|
}
|
|
|
|
CPUARMState *cpu_arm_init(void)
|
|
{
|
|
CPUARMState *env;
|
|
|
|
cpu_exec_init();
|
|
|
|
env = malloc(sizeof(CPUARMState));
|
|
if (!env)
|
|
return NULL;
|
|
memset(env, 0, sizeof(CPUARMState));
|
|
cpu_single_env = env;
|
|
return env;
|
|
}
|
|
|
|
void cpu_arm_close(CPUARMState *env)
|
|
{
|
|
free(env);
|
|
}
|
|
|
|
void cpu_arm_dump_state(CPUARMState *env, FILE *f, int flags)
|
|
{
|
|
int i;
|
|
|
|
for(i=0;i<16;i++) {
|
|
fprintf(f, "R%02d=%08x", i, env->regs[i]);
|
|
if ((i % 4) == 3)
|
|
fprintf(f, "\n");
|
|
else
|
|
fprintf(f, " ");
|
|
}
|
|
fprintf(f, "PSR=%08x %c%c%c%c\n",
|
|
env->cpsr,
|
|
env->cpsr & (1 << 31) ? 'N' : '-',
|
|
env->cpsr & (1 << 30) ? 'Z' : '-',
|
|
env->cpsr & (1 << 29) ? 'C' : '-',
|
|
env->cpsr & (1 << 28) ? 'V' : '-');
|
|
}
|
|
|
|
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
|
|
{
|
|
return addr;
|
|
}
|