135 lines
3.6 KiB
C
135 lines
3.6 KiB
C
/*
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* QEMU emulation of common X86 IOMMU
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*
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* Copyright (C) 2016 Peter Xu, Red Hat <peterx@redhat.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/boards.h"
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#include "hw/i386/x86-iommu.h"
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#include "qemu/error-report.h"
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#include "trace.h"
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void x86_iommu_iec_register_notifier(X86IOMMUState *iommu,
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iec_notify_fn fn, void *data)
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{
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IEC_Notifier *notifier = g_new0(IEC_Notifier, 1);
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notifier->iec_notify = fn;
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notifier->private = data;
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QLIST_INSERT_HEAD(&iommu->iec_notifiers, notifier, list);
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}
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void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global,
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uint32_t index, uint32_t mask)
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{
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IEC_Notifier *notifier;
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trace_x86_iommu_iec_notify(global, index, mask);
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QLIST_FOREACH(notifier, &iommu->iec_notifiers, list) {
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if (notifier->iec_notify) {
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notifier->iec_notify(notifier->private, global,
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index, mask);
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}
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}
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}
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/* Default X86 IOMMU device */
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static X86IOMMUState *x86_iommu_default = NULL;
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static void x86_iommu_set_default(X86IOMMUState *x86_iommu)
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{
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assert(x86_iommu);
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if (x86_iommu_default) {
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error_report("QEMU does not support multiple vIOMMUs "
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"for x86 yet.");
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exit(1);
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}
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x86_iommu_default = x86_iommu;
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}
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X86IOMMUState *x86_iommu_get_default(void)
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{
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return x86_iommu_default;
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}
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IommuType x86_iommu_get_type(void)
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{
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return x86_iommu_default->type;
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}
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static void x86_iommu_realize(DeviceState *dev, Error **errp)
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{
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X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev);
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X86IOMMUClass *x86_class = X86_IOMMU_GET_CLASS(dev);
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QLIST_INIT(&x86_iommu->iec_notifiers);
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if (x86_class->realize) {
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x86_class->realize(dev, errp);
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}
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x86_iommu_set_default(X86_IOMMU_DEVICE(dev));
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}
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static void x86_iommu_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = x86_iommu_realize;
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}
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static bool x86_iommu_intremap_prop_get(Object *o, Error **errp)
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{
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X86IOMMUState *s = X86_IOMMU_DEVICE(o);
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return s->intr_supported;
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}
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static void x86_iommu_intremap_prop_set(Object *o, bool value, Error **errp)
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{
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X86IOMMUState *s = X86_IOMMU_DEVICE(o);
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s->intr_supported = value;
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}
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static void x86_iommu_instance_init(Object *o)
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{
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X86IOMMUState *s = X86_IOMMU_DEVICE(o);
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/* By default, do not support IR */
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s->intr_supported = false;
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object_property_add_bool(o, "intremap", x86_iommu_intremap_prop_get,
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x86_iommu_intremap_prop_set, NULL);
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}
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static const TypeInfo x86_iommu_info = {
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.name = TYPE_X86_IOMMU_DEVICE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_init = x86_iommu_instance_init,
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.instance_size = sizeof(X86IOMMUState),
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.class_init = x86_iommu_class_init,
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.class_size = sizeof(X86IOMMUClass),
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.abstract = true,
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};
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static void x86_iommu_register_types(void)
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{
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type_register_static(&x86_iommu_info);
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}
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type_init(x86_iommu_register_types)
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