qemu-irix/target
David Hildenbrand 2bcf018340 s390x/tcg: low-address protection support
This is a neat way to implement low address protection, whereby
only the first 512 bytes of the first two pages (each 4096 bytes) of
every address space are protected.

Store a tec of 0 for the access exception, this is what is defined by
Enhanced Suppression on Protection in case of a low address protection
(Bit 61 set to 0, rest undefined).

We have to make sure to to pass the access address, not the masked page
address into mmu_translate*().

Drop the check from testblock. So we can properly test this via
kvm-unit-tests.

This will check every access going through one of the MMUs.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20171016202358.3633-3-david@redhat.com>
[CH: restored error message for access register mode]
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20 13:32:10 +02:00
..
alpha tcg: remove addr argument from lookup_tb_ptr 2017-10-10 07:37:10 -07:00
arm target/arm: Implement SG instruction corner cases 2017-10-12 13:23:14 +01:00
cris
hppa tcg: remove addr argument from lookup_tb_ptr 2017-10-10 07:37:10 -07:00
i386 target/i386: trap on instructions longer than >15 bytes 2017-10-16 18:03:53 +02:00
lm32
m68k
microblaze
mips linux-user: Tidy and enforce reserved_va initialization 2017-10-16 16:00:56 +03:00
moxie
nios2 * TCG 8-byte atomic accesses bugfix (Andrew) 2017-10-19 15:38:07 +01:00
openrisc
ppc * TCG 8-byte atomic accesses bugfix (Andrew) 2017-10-19 15:38:07 +01:00
s390x s390x/tcg: low-address protection support 2017-10-20 13:32:10 +02:00
sh4 linux-user/sh4: Reduce TARGET_VIRT_ADDR_SPACE_BITS to 31 2017-10-16 16:00:56 +03:00
sparc
tilegx
tricore
unicore32
xtensa