123 lines
3.8 KiB
C
123 lines
3.8 KiB
C
/*
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* SuperH on-chip PCIC emulation.
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*
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* Copyright (c) 2008 Takashi YOSHII
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "sh.h"
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#include "pci.h"
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#include "pci_host.h"
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#include "sh_pci.h"
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#include "bswap.h"
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typedef struct {
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PCIBus *bus;
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PCIDevice *dev;
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uint32_t par;
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uint32_t mbr;
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uint32_t iobr;
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} SHPCIC;
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static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
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{
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SHPCIC *pcic = p;
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switch(addr) {
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case 0 ... 0xfc:
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cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
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break;
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case 0x1c0:
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pcic->par = val;
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break;
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case 0x1c4:
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pcic->mbr = val & 0xff000001;
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break;
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case 0x1c8:
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if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) {
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cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000,
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IO_MEM_UNASSIGNED);
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pcic->iobr = val & 0xfffc0001;
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isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000);
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}
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break;
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case 0x220:
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pci_data_write(pcic->bus, pcic->par, val, 4);
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break;
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}
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}
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static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
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{
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SHPCIC *pcic = p;
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switch(addr) {
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case 0 ... 0xfc:
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return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
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case 0x1c0:
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return pcic->par;
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case 0x1c4:
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return pcic->mbr;
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case 0x1c8:
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return pcic->iobr;
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case 0x220:
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return pci_data_read(pcic->bus, pcic->par, 4);
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}
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return 0;
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}
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typedef struct {
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CPUReadMemoryFunc * const r[3];
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CPUWriteMemoryFunc * const w[3];
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} MemOp;
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static MemOp sh_pci_reg = {
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{ NULL, NULL, sh_pci_reg_read },
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{ NULL, NULL, sh_pci_reg_write },
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};
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PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *opaque, int devfn_min, int nirq)
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{
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SHPCIC *p;
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int reg;
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p = qemu_mallocz(sizeof(SHPCIC));
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p->bus = pci_register_bus(NULL, "pci",
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set_irq, map_irq, opaque, devfn_min, nirq);
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p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
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-1, NULL, NULL);
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reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p,
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DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(0x1e200000, 0x224, reg);
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cpu_register_physical_memory(0xfe200000, 0x224, reg);
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p->iobr = 0xfe240000;
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isa_mmio_init(p->iobr, 0x40000);
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pci_config_set_vendor_id(p->dev->config, PCI_VENDOR_ID_HITACHI);
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pci_config_set_device_id(p->dev->config, PCI_DEVICE_ID_HITACHI_SH7751R);
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p->dev->config[0x04] = 0x80;
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p->dev->config[0x05] = 0x00;
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p->dev->config[0x06] = 0x90;
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p->dev->config[0x07] = 0x02;
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return p->bus;
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}
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