qemu-irix/target
Eduardo Habkost 61efbbf869 i386: Add new -IBRS versions of Intel CPU models
The new MSR IA32_SPEC_CTRL MSR was introduced by a recent Intel
microcode updated and can be used by OSes to mitigate
CVE-2017-5715.  Unfortunately we can't change the existing CPU
models without breaking existing setups, so users need to
explicitly update their VM configuration to use the new *-IBRS
CPU model if they want to expose IBRS to guests.

The new CPU models are simple copies of the existing CPU models,
with just CPUID_7_0_EDX_SPEC_CTRL added and model_id updated.

Cc: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20180109154519.25634-6-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
(cherry picked from commit ac96c41354)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
2018-01-23 17:08:04 -06:00
..
alpha x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
arm target/arm: Generate UNDEF for 32-bit Thumb2 insns 2017-12-11 17:11:27 +00:00
cris x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
hppa Capstone disassembler 2017-10-27 08:04:51 +01:00
i386 i386: Add new -IBRS versions of Intel CPU models 2018-01-23 17:08:04 -06:00
lm32 x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
m68k x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
microblaze Capstone disassembler 2017-10-27 08:04:51 +01:00
mips x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
moxie moxie: cleanup cpu type name composition 2017-10-27 16:03:54 +02:00
nios2 Capstone disassembler 2017-10-27 08:04:51 +01:00
openrisc x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
ppc target/ppc: Fix system lockups caused by interrupt_request state corruption 2017-12-05 12:28:42 +11:00
s390x s390x/tcg: fix DIAG 308 with > 1 VCPU (MTTCG) 2017-11-20 09:31:46 +01:00
sh4 target/sh4: fix TCG leak during gusa sequence 2018-01-08 07:52:41 -06:00
sparc linux-user/sparc: Put address for data faults where linux-user expects it 2017-11-07 21:59:18 +02:00
tilegx tcg: Initialize cpu_env generically 2017-10-24 13:53:42 -07:00
tricore x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
unicore32 x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
xtensa x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00