568 lines
18 KiB
C
568 lines
18 KiB
C
/*
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* ARM GICv3 emulation: Redistributor
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*
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* Copyright (c) 2015 Huawei.
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* Copyright (c) 2016 Linaro Limited.
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* Written by Shlomo Pongratz, Peter Maydell
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*
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* This code is licensed under the GPL, version 2 or (at your option)
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* any later version.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "gicv3_internal.h"
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static uint32_t mask_group(GICv3CPUState *cs, MemTxAttrs attrs)
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{
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/* Return a 32-bit mask which should be applied for this set of 32
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* interrupts; each bit is 1 if access is permitted by the
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* combination of attrs.secure and GICR_GROUPR. (GICR_NSACR does
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* not affect config register accesses, unlike GICD_NSACR.)
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*/
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if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) {
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/* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI */
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return cs->gicr_igroupr0;
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}
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return 0xFFFFFFFFU;
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}
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static int gicr_ns_access(GICv3CPUState *cs, int irq)
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{
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/* Return the 2 bit NSACR.NS_access field for this SGI */
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assert(irq < 16);
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return extract32(cs->gicr_nsacr, irq * 2, 2);
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}
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static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
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uint32_t *reg, uint32_t val)
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{
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/* Helper routine to implement writing to a "set-bitmap" register */
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val &= mask_group(cs, attrs);
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*reg |= val;
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gicv3_redist_update(cs);
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}
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static void gicr_write_clear_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
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uint32_t *reg, uint32_t val)
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{
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/* Helper routine to implement writing to a "clear-bitmap" register */
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val &= mask_group(cs, attrs);
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*reg &= ~val;
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gicv3_redist_update(cs);
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}
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static uint32_t gicr_read_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
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uint32_t reg)
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{
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reg &= mask_group(cs, attrs);
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return reg;
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}
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static uint8_t gicr_read_ipriorityr(GICv3CPUState *cs, MemTxAttrs attrs,
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int irq)
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{
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/* Read the value of GICR_IPRIORITYR<n> for the specified interrupt,
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* honouring security state (these are RAZ/WI for Group 0 or Secure
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* Group 1 interrupts).
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*/
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uint32_t prio;
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prio = cs->gicr_ipriorityr[irq];
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if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) {
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if (!(cs->gicr_igroupr0 & (1U << irq))) {
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/* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */
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return 0;
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}
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/* NS view of the interrupt priority */
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prio = (prio << 1) & 0xff;
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}
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return prio;
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}
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static void gicr_write_ipriorityr(GICv3CPUState *cs, MemTxAttrs attrs, int irq,
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uint8_t value)
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{
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/* Write the value of GICD_IPRIORITYR<n> for the specified interrupt,
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* honouring security state (these are RAZ/WI for Group 0 or Secure
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* Group 1 interrupts).
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*/
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if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) {
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if (!(cs->gicr_igroupr0 & (1U << irq))) {
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/* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */
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return;
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}
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/* NS view of the interrupt priority */
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value = 0x80 | (value >> 1);
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}
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cs->gicr_ipriorityr[irq] = value;
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}
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static MemTxResult gicr_readb(GICv3CPUState *cs, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{
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switch (offset) {
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case GICR_IPRIORITYR ... GICR_IPRIORITYR + 0x1f:
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*data = gicr_read_ipriorityr(cs, attrs, offset - GICR_IPRIORITYR);
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return MEMTX_OK;
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default:
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return MEMTX_ERROR;
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}
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}
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static MemTxResult gicr_writeb(GICv3CPUState *cs, hwaddr offset,
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uint64_t value, MemTxAttrs attrs)
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{
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switch (offset) {
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case GICR_IPRIORITYR ... GICR_IPRIORITYR + 0x1f:
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gicr_write_ipriorityr(cs, attrs, offset - GICR_IPRIORITYR, value);
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gicv3_redist_update(cs);
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return MEMTX_OK;
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default:
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return MEMTX_ERROR;
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}
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}
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static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{
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switch (offset) {
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case GICR_CTLR:
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*data = cs->gicr_ctlr;
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return MEMTX_OK;
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case GICR_IIDR:
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*data = gicv3_iidr();
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return MEMTX_OK;
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case GICR_TYPER:
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*data = extract64(cs->gicr_typer, 0, 32);
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return MEMTX_OK;
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case GICR_TYPER + 4:
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*data = extract64(cs->gicr_typer, 32, 32);
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return MEMTX_OK;
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case GICR_STATUSR:
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/* RAZ/WI for us (this is an optional register and our implementation
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* does not track RO/WO/reserved violations to report them to the guest)
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*/
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*data = 0;
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return MEMTX_OK;
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case GICR_WAKER:
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*data = cs->gicr_waker;
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return MEMTX_OK;
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case GICR_PROPBASER:
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*data = extract64(cs->gicr_propbaser, 0, 32);
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return MEMTX_OK;
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case GICR_PROPBASER + 4:
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*data = extract64(cs->gicr_propbaser, 32, 32);
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return MEMTX_OK;
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case GICR_PENDBASER:
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*data = extract64(cs->gicr_pendbaser, 0, 32);
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return MEMTX_OK;
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case GICR_PENDBASER + 4:
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*data = extract64(cs->gicr_pendbaser, 32, 32);
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return MEMTX_OK;
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case GICR_IGROUPR0:
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if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) {
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*data = 0;
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return MEMTX_OK;
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}
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*data = cs->gicr_igroupr0;
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return MEMTX_OK;
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case GICR_ISENABLER0:
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case GICR_ICENABLER0:
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*data = gicr_read_bitmap_reg(cs, attrs, cs->gicr_ienabler0);
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return MEMTX_OK;
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case GICR_ISPENDR0:
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case GICR_ICPENDR0:
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{
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/* The pending register reads as the logical OR of the pending
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* latch and the input line level for level-triggered interrupts.
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*/
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uint32_t val = cs->gicr_ipendr0 | (~cs->edge_trigger & cs->level);
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*data = gicr_read_bitmap_reg(cs, attrs, val);
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return MEMTX_OK;
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}
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case GICR_ISACTIVER0:
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case GICR_ICACTIVER0:
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*data = gicr_read_bitmap_reg(cs, attrs, cs->gicr_iactiver0);
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return MEMTX_OK;
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case GICR_IPRIORITYR ... GICR_IPRIORITYR + 0x1f:
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{
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int i, irq = offset - GICR_IPRIORITYR;
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uint32_t value = 0;
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for (i = irq + 3; i >= irq; i--, value <<= 8) {
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value |= gicr_read_ipriorityr(cs, attrs, i);
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}
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*data = value;
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return MEMTX_OK;
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}
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case GICR_ICFGR0:
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case GICR_ICFGR1:
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{
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/* Our edge_trigger bitmap is one bit per irq; take the correct
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* half of it, and spread it out into the odd bits.
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*/
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uint32_t value;
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value = cs->edge_trigger & mask_group(cs, attrs);
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value = extract32(value, (offset == GICR_ICFGR1) ? 16 : 0, 16);
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value = half_shuffle32(value) << 1;
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*data = value;
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return MEMTX_OK;
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}
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case GICR_IGRPMODR0:
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if ((cs->gic->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
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/* RAZ/WI if security disabled, or if
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* security enabled and this is an NS access
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*/
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*data = 0;
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return MEMTX_OK;
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}
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*data = cs->gicr_igrpmodr0;
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return MEMTX_OK;
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case GICR_NSACR:
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if ((cs->gic->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
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/* RAZ/WI if security disabled, or if
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* security enabled and this is an NS access
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*/
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*data = 0;
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return MEMTX_OK;
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}
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*data = cs->gicr_nsacr;
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return MEMTX_OK;
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case GICR_IDREGS ... GICR_IDREGS + 0x1f:
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*data = gicv3_idreg(offset - GICR_IDREGS);
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return MEMTX_OK;
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default:
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return MEMTX_ERROR;
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}
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}
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static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
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uint64_t value, MemTxAttrs attrs)
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{
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switch (offset) {
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case GICR_CTLR:
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/* For our implementation, GICR_TYPER.DPGS is 0 and so all
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* the DPG bits are RAZ/WI. We don't do anything asynchronously,
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* so UWP and RWP are RAZ/WI. And GICR_TYPER.LPIS is 0 (we don't
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* implement LPIs) so Enable_LPIs is RES0. So there are no writable
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* bits for us.
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*/
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return MEMTX_OK;
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case GICR_STATUSR:
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/* RAZ/WI for our implementation */
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return MEMTX_OK;
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case GICR_WAKER:
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/* Only the ProcessorSleep bit is writeable. When the guest sets
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* it it requests that we transition the channel between the
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* redistributor and the cpu interface to quiescent, and that
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* we set the ChildrenAsleep bit once the inteface has reached the
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* quiescent state.
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* Setting the ProcessorSleep to 0 reverses the quiescing, and
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* ChildrenAsleep is cleared once the transition is complete.
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* Since our interface is not asynchronous, we complete these
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* transitions instantaneously, so we set ChildrenAsleep to the
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* same value as ProcessorSleep here.
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*/
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value &= GICR_WAKER_ProcessorSleep;
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if (value & GICR_WAKER_ProcessorSleep) {
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value |= GICR_WAKER_ChildrenAsleep;
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}
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cs->gicr_waker = value;
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return MEMTX_OK;
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case GICR_PROPBASER:
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cs->gicr_propbaser = deposit64(cs->gicr_propbaser, 0, 32, value);
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return MEMTX_OK;
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case GICR_PROPBASER + 4:
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cs->gicr_propbaser = deposit64(cs->gicr_propbaser, 32, 32, value);
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return MEMTX_OK;
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case GICR_PENDBASER:
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cs->gicr_pendbaser = deposit64(cs->gicr_pendbaser, 0, 32, value);
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return MEMTX_OK;
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case GICR_PENDBASER + 4:
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cs->gicr_pendbaser = deposit64(cs->gicr_pendbaser, 32, 32, value);
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return MEMTX_OK;
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case GICR_IGROUPR0:
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if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) {
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return MEMTX_OK;
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}
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cs->gicr_igroupr0 = value;
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gicv3_redist_update(cs);
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return MEMTX_OK;
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case GICR_ISENABLER0:
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gicr_write_set_bitmap_reg(cs, attrs, &cs->gicr_ienabler0, value);
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return MEMTX_OK;
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case GICR_ICENABLER0:
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gicr_write_clear_bitmap_reg(cs, attrs, &cs->gicr_ienabler0, value);
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return MEMTX_OK;
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case GICR_ISPENDR0:
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gicr_write_set_bitmap_reg(cs, attrs, &cs->gicr_ipendr0, value);
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return MEMTX_OK;
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case GICR_ICPENDR0:
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gicr_write_clear_bitmap_reg(cs, attrs, &cs->gicr_ipendr0, value);
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return MEMTX_OK;
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case GICR_ISACTIVER0:
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gicr_write_set_bitmap_reg(cs, attrs, &cs->gicr_iactiver0, value);
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return MEMTX_OK;
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case GICR_ICACTIVER0:
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gicr_write_clear_bitmap_reg(cs, attrs, &cs->gicr_iactiver0, value);
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return MEMTX_OK;
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case GICR_IPRIORITYR ... GICR_IPRIORITYR + 0x1f:
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{
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int i, irq = offset - GICR_IPRIORITYR;
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for (i = irq; i < irq + 4; i++, value >>= 8) {
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gicr_write_ipriorityr(cs, attrs, i, value);
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}
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gicv3_redist_update(cs);
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return MEMTX_OK;
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}
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case GICR_ICFGR0:
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/* Register is all RAZ/WI or RAO/WI bits */
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return MEMTX_OK;
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case GICR_ICFGR1:
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{
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uint32_t mask;
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/* Since our edge_trigger bitmap is one bit per irq, our input
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* 32-bits will compress down into 16 bits which we need
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* to write into the bitmap.
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*/
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value = half_unshuffle32(value >> 1) << 16;
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mask = mask_group(cs, attrs) & 0xffff0000U;
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cs->edge_trigger &= ~mask;
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cs->edge_trigger |= (value & mask);
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gicv3_redist_update(cs);
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return MEMTX_OK;
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}
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case GICR_IGRPMODR0:
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if ((cs->gic->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
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/* RAZ/WI if security disabled, or if
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* security enabled and this is an NS access
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*/
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return MEMTX_OK;
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}
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cs->gicr_igrpmodr0 = value;
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gicv3_redist_update(cs);
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return MEMTX_OK;
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case GICR_NSACR:
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if ((cs->gic->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
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/* RAZ/WI if security disabled, or if
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* security enabled and this is an NS access
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*/
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return MEMTX_OK;
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}
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cs->gicr_nsacr = value;
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/* no update required as this only affects access permission checks */
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return MEMTX_OK;
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case GICR_IIDR:
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case GICR_TYPER:
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case GICR_IDREGS ... GICR_IDREGS + 0x1f:
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/* RO registers, ignore the write */
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid guest write to RO register at offset "
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TARGET_FMT_plx "\n", __func__, offset);
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return MEMTX_OK;
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default:
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return MEMTX_ERROR;
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}
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}
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static MemTxResult gicr_readll(GICv3CPUState *cs, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{
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switch (offset) {
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case GICR_TYPER:
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*data = cs->gicr_typer;
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return MEMTX_OK;
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case GICR_PROPBASER:
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*data = cs->gicr_propbaser;
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return MEMTX_OK;
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case GICR_PENDBASER:
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*data = cs->gicr_pendbaser;
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return MEMTX_OK;
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default:
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return MEMTX_ERROR;
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}
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}
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static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr offset,
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uint64_t value, MemTxAttrs attrs)
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{
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switch (offset) {
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case GICR_PROPBASER:
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cs->gicr_propbaser = value;
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return MEMTX_OK;
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case GICR_PENDBASER:
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cs->gicr_pendbaser = value;
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return MEMTX_OK;
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case GICR_TYPER:
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/* RO register, ignore the write */
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid guest write to RO register at offset "
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TARGET_FMT_plx "\n", __func__, offset);
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return MEMTX_OK;
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default:
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return MEMTX_ERROR;
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}
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}
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MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
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unsigned size, MemTxAttrs attrs)
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{
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GICv3State *s = opaque;
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GICv3CPUState *cs;
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MemTxResult r;
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int cpuidx;
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assert((offset & (size - 1)) == 0);
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/* This region covers all the redistributor pages; there are
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* (for GICv3) two 64K pages per CPU. At the moment they are
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* all contiguous (ie in this one region), though we might later
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* want to allow splitting of redistributor pages into several
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* blocks so we can support more CPUs.
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*/
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cpuidx = offset / 0x20000;
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offset %= 0x20000;
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assert(cpuidx < s->num_cpu);
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cs = &s->cpu[cpuidx];
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switch (size) {
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case 1:
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r = gicr_readb(cs, offset, data, attrs);
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break;
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case 4:
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r = gicr_readl(cs, offset, data, attrs);
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break;
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case 8:
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r = gicr_readll(cs, offset, data, attrs);
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break;
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default:
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r = MEMTX_ERROR;
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break;
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}
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if (r == MEMTX_ERROR) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid guest read at offset " TARGET_FMT_plx
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"size %u\n", __func__, offset, size);
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trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,
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size, attrs.secure);
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} else {
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trace_gicv3_redist_read(gicv3_redist_affid(cs), offset, *data,
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size, attrs.secure);
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}
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return r;
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}
|
|
|
|
MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
|
|
unsigned size, MemTxAttrs attrs)
|
|
{
|
|
GICv3State *s = opaque;
|
|
GICv3CPUState *cs;
|
|
MemTxResult r;
|
|
int cpuidx;
|
|
|
|
assert((offset & (size - 1)) == 0);
|
|
|
|
/* This region covers all the redistributor pages; there are
|
|
* (for GICv3) two 64K pages per CPU. At the moment they are
|
|
* all contiguous (ie in this one region), though we might later
|
|
* want to allow splitting of redistributor pages into several
|
|
* blocks so we can support more CPUs.
|
|
*/
|
|
cpuidx = offset / 0x20000;
|
|
offset %= 0x20000;
|
|
assert(cpuidx < s->num_cpu);
|
|
|
|
cs = &s->cpu[cpuidx];
|
|
|
|
switch (size) {
|
|
case 1:
|
|
r = gicr_writeb(cs, offset, data, attrs);
|
|
break;
|
|
case 4:
|
|
r = gicr_writel(cs, offset, data, attrs);
|
|
break;
|
|
case 8:
|
|
r = gicr_writell(cs, offset, data, attrs);
|
|
break;
|
|
default:
|
|
r = MEMTX_ERROR;
|
|
break;
|
|
}
|
|
|
|
if (r == MEMTX_ERROR) {
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"%s: invalid guest write at offset " TARGET_FMT_plx
|
|
"size %u\n", __func__, offset, size);
|
|
trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,
|
|
size, attrs.secure);
|
|
} else {
|
|
trace_gicv3_redist_write(gicv3_redist_affid(cs), offset, data,
|
|
size, attrs.secure);
|
|
}
|
|
return r;
|
|
}
|
|
|
|
void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level)
|
|
{
|
|
/* Update redistributor state for a change in an external PPI input line */
|
|
if (level == extract32(cs->level, irq, 1)) {
|
|
return;
|
|
}
|
|
|
|
trace_gicv3_redist_set_irq(gicv3_redist_affid(cs), irq, level);
|
|
|
|
cs->level = deposit32(cs->level, irq, 1, level);
|
|
|
|
if (level) {
|
|
/* 0->1 edges latch the pending bit for edge-triggered interrupts */
|
|
if (extract32(cs->edge_trigger, irq, 1)) {
|
|
cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 1);
|
|
}
|
|
}
|
|
|
|
gicv3_redist_update(cs);
|
|
}
|
|
|
|
void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns)
|
|
{
|
|
/* Update redistributor state for a generated SGI */
|
|
int irqgrp = gicv3_irq_group(cs->gic, cs, irq);
|
|
|
|
/* If we are asked for a Secure Group 1 SGI and it's actually
|
|
* configured as Secure Group 0 this is OK (subject to the usual
|
|
* NSACR checks).
|
|
*/
|
|
if (grp == GICV3_G1 && irqgrp == GICV3_G0) {
|
|
grp = GICV3_G0;
|
|
}
|
|
|
|
if (grp != irqgrp) {
|
|
return;
|
|
}
|
|
|
|
if (ns && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) {
|
|
/* If security is enabled we must test the NSACR bits */
|
|
int nsaccess = gicr_ns_access(cs, irq);
|
|
|
|
if ((irqgrp == GICV3_G0 && nsaccess < 1) ||
|
|
(irqgrp == GICV3_G1 && nsaccess < 2)) {
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* OK, we can accept the SGI */
|
|
trace_gicv3_redist_send_sgi(gicv3_redist_affid(cs), irq);
|
|
cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 1);
|
|
gicv3_redist_update(cs);
|
|
}
|